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From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 13 Feb 2018 14:27:44 +0000
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Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v2 00/32] Add ARMv8.2
 half-precision functions
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To: =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>

On 8 February 2018 at 17:31, Alex Benn=C3=A9e <alex.bennee@linaro.org> wrot=
e:
> Hi,
>
> Some of this was posted before as part of the various partial patch
> series when we first started messing around with FP16 in softfloat.
> This series is now just the ARM bits and expects to have the V4
> softfloat patches as a prerequisite:
>
>   https://lists.nongnu.org/archive/html/qemu-devel/2018-02/msg01330.html
>
> Alternatively you can grab the full tree from:
>
>   https://github.com/stsquad/qemu/tree/arm-fp16-v2
>
> I've tested with the following RISU test binaries:
>
>   http://people.linaro.org/~alex.bennee/testcases/arm64.risu/testcases.ar=
mv8.2_hp.tar.xz
>
> And of course I ran the original RISU tests with:
>
>   -cpu any,fp16=3Doff
>
> But I guess we really just need to carefully regenerate the testcases
> to not include UNDEF's which get added with future revisions of the
> specification.
>
> Anyway please review.

I see Richard's reviewed this one, so I just had the one comment
about feature flag naming. Could you also fix the checkpatch long-lines
warnings and look at whatever the problem that caused patchew build
failures is, please?

thanks
-- PMM