qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL 00/18] target-arm queue
Date: Thu, 1 Oct 2020 19:45:05 +0100	[thread overview]
Message-ID: <CAFEAcA_vcLOkoUHL0k-aUdf2DZaofnHLnTDPstexQoS1bB7Xdw@mail.gmail.com> (raw)
In-Reply-To: <20201001144759.5964-1-peter.maydell@linaro.org>

On Thu, 1 Oct 2020 at 15:48, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Nothing very exciting this time around...
>
> -- PMM
>
> The following changes since commit 37a712a0f969ca2df7f01182409a6c4825cebfb5:
>
>   Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-10-01 12:23:19 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201001
>
> for you to fetch changes up to cdfaa57dcb53ba012439765a1462247dfda8595d:
>
>   hw/arm/raspi: Remove use of the 'version' value in the board code (2020-10-01 15:31:01 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * Make isar_feature_aa32_fp16_arith() handle M-profile
>  * Fix SVE splice
>  * Fix SVE LDR/STR
>  * Remove ignore_memory_transaction_failures on the raspi2
>  * raspi: Various cleanup/refactoring


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.

-- PMM


  parent reply	other threads:[~2020-10-01 18:46 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-01 14:47 [PULL 00/18] target-arm queue Peter Maydell
2020-10-01 14:47 ` [PULL 01/18] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check Peter Maydell
2020-10-01 14:47 ` [PULL 02/18] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters Peter Maydell
2020-10-01 14:47 ` [PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs Peter Maydell
2020-10-01 14:47 ` [PULL 04/18] target/arm: Add ID register values for Cortex-M0 Peter Maydell
2020-10-01 14:47 ` [PULL 05/18] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile Peter Maydell
2020-10-01 14:47 ` [PULL 06/18] target/arm: Fix sve ldr/str Peter Maydell
2020-10-01 14:47 ` [PULL 07/18] target/arm: Fix SVE splice Peter Maydell
2020-10-01 14:47 ` [PULL 08/18] hw/arm/raspi: Define various blocks base addresses Peter Maydell
2020-10-01 14:47 ` [PULL 09/18] hw/arm/bcm2835: Add more unimplemented peripherals Peter Maydell
2020-10-01 14:47 ` [PULL 10/18] hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2 Peter Maydell
2020-10-01 14:47 ` [PULL 11/18] hw/arm/raspi: Display the board revision in the machine description Peter Maydell
2020-10-01 14:47 ` [PULL 12/18] hw/arm/raspi: Load the firmware on the first core Peter Maydell
2020-10-01 14:47 ` [PULL 13/18] hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState Peter Maydell
2020-10-01 14:47 ` [PULL 14/18] hw/arm/raspi: Avoid using TypeInfo::class_data pointer Peter Maydell
2020-10-01 14:47 ` [PULL 15/18] hw/arm/raspi: Use more specific machine names Peter Maydell
2020-10-01 14:47 ` [PULL 16/18] hw/arm/raspi: Introduce RaspiProcessorId enum Peter Maydell
2020-10-01 14:47 ` [PULL 17/18] hw/arm/raspi: Use RaspiProcessorId to set the firmware load address Peter Maydell
2020-10-01 14:47 ` [PULL 18/18] hw/arm/raspi: Remove use of the 'version' value in the board code Peter Maydell
2020-10-01 18:45 ` Peter Maydell [this message]
  -- strict thread matches above, loose matches on Subject: below --
2022-03-07 16:46 [PULL 00/18] target-arm queue Peter Maydell
2022-03-08 17:08 ` Peter Maydell
2024-06-22 12:06 Peter Maydell
2024-06-23 17:46 ` Richard Henderson
2024-10-29 15:10 Peter Maydell
2024-10-31 16:33 ` Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAFEAcA_vcLOkoUHL0k-aUdf2DZaofnHLnTDPstexQoS1bB7Xdw@mail.gmail.com \
    --to=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).