From: Peter Maydell <peter.maydell@linaro.org>
To: Roman Kapl <rka@sysgo.com>
Cc: qemu-arm <qemu-arm@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>,
Jean-Christophe Dubois <jcd@tribudubois.net>
Subject: Re: [PATCH] i.MX: Fix inverted register bits in wdt code.
Date: Tue, 11 Feb 2020 17:57:39 +0000 [thread overview]
Message-ID: <CAFEAcA_vgg8mVw+-vfjWcouyOOnM_qZPdsPFmSgatV4Lq5Panw@mail.gmail.com> (raw)
In-Reply-To: <20200207095409.11227-1-rka@sysgo.com>
On Fri, 7 Feb 2020 at 09:55, Roman Kapl <rka@sysgo.com> wrote:
>
> Documentation says for WDA '0: Assert WDOG output.' and for SRS
> '0: Assert system reset signal.'.
>
> Signed-off-by: Roman Kapl <rka@sysgo.com>
> ---
> hw/misc/imx2_wdt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to target-arm.next, thanks.
(It looks like we're missing a lot of the watchdog
functionality in our model, ie the actual watchdog
timer parts, enable bits, etc etc...)
-- PMM
next prev parent reply other threads:[~2020-02-11 17:58 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-07 9:54 [PATCH] i.MX: Fix inverted register bits in wdt code Roman Kapl
2020-02-11 17:57 ` Peter Maydell [this message]
2020-02-12 9:10 ` Roman Kapl
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