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From: Peter Maydell <peter.maydell@linaro.org>
Date: Mon, 27 Jan 2014 17:43:12 +0000
Message-ID: <CAFEAcA_wY+RWE+DcL3013ON8vx2nxMBKU-itzT20KOLru+-aMA@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PATCH target-arm v5 3/5] zynq_slcr: Implement CPU
	reset
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To: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: Edgar Iglesias <edgar.iglesias@xilinx.com>, QEMU Developers <qemu-devel@nongnu.org>, Alistair Francis <alistair.francis@xilinx.com>

On 15 January 2014 09:14, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> Implement the CPU reset IO line of the A9_CPU_RST_CTRL register
> (offset 0x244). This is trivial GPIO mapping straight to the register
> bits.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM