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From: Peter Maydell <peter.maydell@linaro.org>
To: Fabian Aggeler <aggelerf@ethz.ch>
Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v2] target-arm: implement CPACR register logic for ARMv7
Date: Fri, 23 May 2014 14:14:28 +0100	[thread overview]
Message-ID: <CAFEAcA_ys2hnih16vQawsQOELFQBfOLdd1zUe6wz0PDSMdO1hw@mail.gmail.com> (raw)
In-Reply-To: <1400532968-30668-1-git-send-email-aggelerf@ethz.ch>

On 19 May 2014 21:56, Fabian Aggeler <aggelerf@ethz.ch> wrote:
> In ARMv7 the CPACR register allows to control access rights to
> coprocessor 0-13 interfaces. Bits corresponding to unimplemented
> coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are
> UNK/SBZP if VFP is not implemented and RAO/WI in some cases.
> Treating TRCDIS as RAZ/WI since we neither implement a trace
> macrocell nor a CP14 interface to the trace macrocell registers.
>
> Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN
> bit in the TB flags, flushing the TLB is not necessary anymore.
>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> ---

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

I'll add this into the target-arm.next tree.

thanks
-- PMM

      reply	other threads:[~2014-05-23 13:14 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-19 20:56 [Qemu-devel] [PATCH v2] target-arm: implement CPACR register logic for ARMv7 Fabian Aggeler
2014-05-23 13:14 ` Peter Maydell [this message]

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