[Qemu-devel] [PATCH v2] target-arm: implement CPACR register logic for ARMv7

[Qemu-devel] [PATCH v2] target-arm: implement CPACR register logic for ARMv7

[Fabian Aggeler]

In ARMv7 the CPACR register allows to control access rights to
coprocessor 0-13 interfaces. Bits corresponding to unimplemented
coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are
UNK/SBZP if VFP is not implemented and RAO/WI in some cases.
Treating TRCDIS as RAZ/WI since we neither implement a trace
macrocell nor a CP14 interface to the trace macrocell registers.

Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN
bit in the TB flags, flushing the TLB is not necessary anymore.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
---
v1 -> v2:
* Removed unnecessary checks in disas_coproc_insn()
* Made changes in cpacr_write() ARMv7 specific
* Accounting for ASEDIS, D32DIS and TRCDIS bits

 target-arm/helper.c | 32 ++++++++++++++++++++++++++++----
 1 file changed, 28 insertions(+), 4 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 417161e..cb59f00 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -477,11 +477,35 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
 {
-    if (env->cp15.c1_coproc != value) {
-        env->cp15.c1_coproc = value;
-        /* ??? Is this safe when called from within a TB?  */
-        tb_flush(env);
+    uint32_t mask = 0;
+
+    /* In ARMv8 most bits of CPACR_EL1 are RES0. */
+    if (!arm_feature(env, ARM_FEATURE_V8)) {
+        /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
+         * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
+         * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
+         */
+        if (arm_feature(env, ARM_FEATURE_VFP)) {
+            /* VFP coprocessor: cp10 & cp11 [23:20] */
+            mask |= (1 << 31) | (1 << 30) | (0xf << 20);
+
+            if (!arm_feature(env, ARM_FEATURE_NEON)) {
+                /* ASEDIS [31] bit is RAO/WI */
+                value |= (1 << 31);
+            }
+
+            /* VFPv3 and upwards with NEON implement 32 double precision
+             * registers (D0-D31).
+             */
+            if (!arm_feature(env, ARM_FEATURE_NEON) ||
+                    !arm_feature(env, ARM_FEATURE_VFP3)) {
+                /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
+                value |= (1 << 30);
+            }
+        }
+        value &= mask;
     }
+    env->cp15.c1_coproc = value;
 }
 
 static const ARMCPRegInfo v6_cp_reginfo[] = {
-- 
1.8.3.2

Re: [Qemu-devel] [PATCH v2] target-arm: implement CPACR register logic for ARMv7

[Peter Maydell]

On 19 May 2014 21:56, Fabian Aggeler <aggelerf@ethz.ch> wrote:
> In ARMv7 the CPACR register allows to control access rights to
> coprocessor 0-13 interfaces. Bits corresponding to unimplemented
> coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are
> UNK/SBZP if VFP is not implemented and RAO/WI in some cases.
> Treating TRCDIS as RAZ/WI since we neither implement a trace
> macrocell nor a CP14 interface to the trace macrocell registers.
>
> Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN
> bit in the TB flags, flushing the TLB is not necessary anymore.
>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> ---

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

I'll add this into the target-arm.next tree.

thanks
-- PMM