From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41285) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnpJG-0000Jy-FD for qemu-devel@nongnu.org; Fri, 23 May 2014 09:14:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WnpJC-00060l-48 for qemu-devel@nongnu.org; Fri, 23 May 2014 09:14:54 -0400 Received: from mail-la0-f53.google.com ([209.85.215.53]:34550) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnpJB-0005zP-Th for qemu-devel@nongnu.org; Fri, 23 May 2014 09:14:50 -0400 Received: by mail-la0-f53.google.com with SMTP id ty20so2602246lab.40 for ; Fri, 23 May 2014 06:14:48 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1400532968-30668-1-git-send-email-aggelerf@ethz.ch> References: <1400532968-30668-1-git-send-email-aggelerf@ethz.ch> From: Peter Maydell Date: Fri, 23 May 2014 14:14:28 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH v2] target-arm: implement CPACR register logic for ARMv7 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabian Aggeler Cc: Peter Crosthwaite , QEMU Developers On 19 May 2014 21:56, Fabian Aggeler wrote: > In ARMv7 the CPACR register allows to control access rights to > coprocessor 0-13 interfaces. Bits corresponding to unimplemented > coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are > UNK/SBZP if VFP is not implemented and RAO/WI in some cases. > Treating TRCDIS as RAZ/WI since we neither implement a trace > macrocell nor a CP14 interface to the trace macrocell registers. > > Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN > bit in the TB flags, flushing the TLB is not necessary anymore. > > Signed-off-by: Fabian Aggeler > --- Reviewed-by: Peter Maydell I'll add this into the target-arm.next tree. thanks -- PMM