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From: Peter Maydell <peter.maydell@linaro.org>
To: Victor CLEMENT <victor.clement@openwide.fr>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
	julien.viarddegalbert@openwide.fr
Subject: Re: [Qemu-devel] [PATCH 1/1] pl061: fix wrong calculation of GPIOMIS register
Date: Mon, 1 Jun 2015 18:22:09 +0100	[thread overview]
Message-ID: <CAFEAcA_z7VdmSywp7EzDEL6WDUnie8S5m02k8fYu1qoTAhf88Q@mail.gmail.com> (raw)
In-Reply-To: <1433154824-6927-1-git-send-email-victor.clement@openwide.fr>

On 1 June 2015 at 11:33, Victor CLEMENT <victor.clement@openwide.fr> wrote:
> The masked interrupt status register should be the state of the interrupt
> after masking.
> There should be a logical AND instead of a logical OR between the
> interrupt status and the interrupt mask.
>
> Signed-off-by: Victor CLEMENT <victor.clement@openwide.fr>

Applied, thanks.

-- PMM

      parent reply	other threads:[~2015-06-01 17:22 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-01 10:33 [Qemu-devel] [PATCH 1/1] pl061: fix wrong calculation of GPIOMIS register Victor CLEMENT
2015-06-01 10:47 ` Peter Crosthwaite
2015-06-01 17:22 ` Peter Maydell [this message]

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