From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56120) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzTQ2-0005dR-AF for qemu-devel@nongnu.org; Mon, 01 Jun 2015 13:22:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzTPy-0001jZ-AK for qemu-devel@nongnu.org; Mon, 01 Jun 2015 13:22:34 -0400 Received: from mail-ie0-f169.google.com ([209.85.223.169]:35748) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzTPy-0001jU-6X for qemu-devel@nongnu.org; Mon, 01 Jun 2015 13:22:30 -0400 Received: by iesa3 with SMTP id a3so114361828ies.2 for ; Mon, 01 Jun 2015 10:22:29 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1433154824-6927-1-git-send-email-victor.clement@openwide.fr> References: <1433154824-6927-1-git-send-email-victor.clement@openwide.fr> From: Peter Maydell Date: Mon, 1 Jun 2015 18:22:09 +0100 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH 1/1] pl061: fix wrong calculation of GPIOMIS register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Victor CLEMENT Cc: QEMU Developers , julien.viarddegalbert@openwide.fr On 1 June 2015 at 11:33, Victor CLEMENT wrote: > The masked interrupt status register should be the state of the interrupt > after masking. > There should be a logical AND instead of a logical OR between the > interrupt status and the interrupt mask. > > Signed-off-by: Victor CLEMENT Applied, thanks. -- PMM