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From: Peter Maydell <peter.maydell@linaro.org>
Date: Tue, 12 Jul 2016 13:03:22 +0100
Message-ID: <CAFEAcA_zCmz=axfbOWizTRorcK9GuPGSCiD6_AMuV65+UEC7PQ@mail.gmail.com>
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Subject: Re: [Qemu-devel] [PULL 00/11] target-mips queue
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To: Leon Alrae <leon.alrae@imgtec.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Aurelien Jarno <aurelien@aurel32.net>

On 12 July 2016 at 12:14, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> This pull request adds MIPS CPS features needed to boot MIPSr6 SMP Linux on
> multiple VPs, renames MIPS64R6-generic to I6400 and adds 10-bit ASID support.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit e2c8f9e44e07d8210049abaa6042ec3c956f1dd4:
>
>   Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into staging (2016-07-04 10:49:17 +0100)
>
> are available in the git repository at:
>
>   git://github.com/lalrae/qemu.git tags/mips-20160712
>
> for you to fetch changes up to cdc46fab07a122dfcc8a1054510a68d936ae3440:
>
>   target-mips: enable 10-bit ASIDs in I6400 CPU (2016-07-12 09:10:21 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2016-07-12
>
> Changes:
> * support 10-bit ASIDs
> * MIPS64R6-generic renamed to I6400
> * initial GIC support
> * implement RESET_BASE register in CM GCR
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM