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Thu, 28 Nov 2024 08:30:11 -0500 Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2ff550d37a6so9558831fa.0 for ; Thu, 28 Nov 2024 05:30:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732800608; x=1733405408; darn=nongnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=HdxVcGZn2g90vtNJBwAGz4nBOwK1aqnh7yPSz2Erf7g=; b=zV5IaynCpltkhOifp9j/QXLNO4LJ4NimHLj30mGMcaHdcD7/X24qQuzuJw6xVXPE+1 2tR07S9q+wKLjw07BB2ACzr1wHhefxZ6S8+DjEe4CnTNRJsJicQIEg18E2LDNNPxxYUE dV3L6hhtBOIAYQJF9WV4eRu4ScbW1o9PhIB2UEgUBlhwidPMP/mSjylvk3vp6WH/rYmU h7QkyxsXM/bS93/WcjP4gkxzxYIM47kZioHgIE8LF0VxT9lWXDr8Gicd0myU8bSecOuF D6CO5bzopdhudTUhP4jLqWOGfwudseLyI0tMJ8jtsw72Hd6ujcCXOKGH+6z40xGWVpl6 Qytw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732800608; x=1733405408; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, 2 May 2021 at 15:44, Richard Henderson wrote: > > From: Taylor Simpson > > Suggested-by: Richard Henderson > Signed-off-by: Taylor Simpson > Reviewed-by: Richard Henderson > Message-Id: <1617930474-31979-11-git-send-email-tsimpson@quicinc.com> > Signed-off-by: Richard Henderson > diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc > index c2f87addb2..9ea318f3e2 100644 > --- a/fpu/softfloat-specialize.c.inc > +++ b/fpu/softfloat-specialize.c.inc > @@ -145,6 +145,9 @@ static FloatParts parts_default_nan(float_status *status) > #elif defined(TARGET_HPPA) > /* snan_bit_is_one, set msb-1. */ > frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); > +#elif defined(TARGET_HEXAGON) > + sign = 1; > + frac = ~0ULL; > #else > /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, > * S390, SH4, TriCore, and Xtensa. I cannot find documentation This change has the effect that Hexagon is unique in that its default_nan value doesn't correspond with its setting for snan_bit_is_one(): the default NaN is supposed to be a QNaN but this value is what snan_bit_is_one() thinks is an SNaN. Is that intentional? Should we adjust snan_bit_is_one() too ? (I noticed this because I need to make the default-nan value be runtime-selectable, and was wondering if I could avoid having to make targets specify snan_bit_is_one separately from specifying their default-NaN value. But this handling of Hexagon would prevent that.) thanks -- PMM