From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45893) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnpS2-0005gb-Ud for qemu-devel@nongnu.org; Tue, 03 Dec 2013 07:51:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VnpRx-0002O6-Tj for qemu-devel@nongnu.org; Tue, 03 Dec 2013 07:51:42 -0500 Received: from mail-pb0-f42.google.com ([209.85.160.42]:39609) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnpRx-0002Nu-OH for qemu-devel@nongnu.org; Tue, 03 Dec 2013 07:51:37 -0500 Received: by mail-pb0-f42.google.com with SMTP id uo5so21032559pbc.29 for ; Tue, 03 Dec 2013 04:51:36 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <1386060535-15908-1-git-send-email-s.fedorov@samsung.com> <1386060535-15908-6-git-send-email-s.fedorov@samsung.com> From: Peter Maydell Date: Tue, 3 Dec 2013 12:51:16 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: a.basov@samsung.com, Sergey Fedorov , "qemu-devel@nongnu.org Developers" , Johannes Winter , Svetlana Fedoseeva On 3 December 2013 12:20, Peter Crosthwaite wrote: > On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote: >> From: Svetlana Fedoseeva >> >> Define CPU monitor mode. Adjust core registers banking. Adjust CPU VM >> state info. Provide CPU mode name for monitor mode. >> >> Signed-off-by: Svetlana Fedoseeva >> Signed-off-by: Sergey Fedorov >> --- >> target-arm/cpu.h | 7 ++++--- >> target-arm/helper.c | 3 +++ >> target-arm/machine.c | 12 ++++++------ >> target-arm/translate.c | 2 +- >> 4 files changed, 14 insertions(+), 10 deletions(-) >> >> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >> index 0b93e39..94d8bd1 100644 >> --- a/target-arm/cpu.h >> +++ b/target-arm/cpu.h >> @@ -124,9 +124,9 @@ typedef struct CPUARMState { >> uint32_t spsr; >> >> /* Banked registers. */ >> - uint32_t banked_spsr[6]; >> - uint32_t banked_r13[6]; >> - uint32_t banked_r14[6]; >> + uint32_t banked_spsr[7]; >> + uint32_t banked_r13[7]; >> + uint32_t banked_r14[7]; >> > > Are there any more modes yet to be implemented? It might save on > future VMSD version bumps if we just pad this out to its ultimate > value now. The remaining mode defined for AArch32 which we don't implement yet is Hyp mode, which has a banked R13 and SPSR, but not a banked LR. -- PMM