* Heterogeneous/AMP example in mainline?
@ 2020-09-18 13:06 karthik poduval
2020-09-18 15:08 ` Peter Maydell
0 siblings, 1 reply; 3+ messages in thread
From: karthik poduval @ 2020-09-18 13:06 UTC (permalink / raw)
To: qemu-devel
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Hi All,
Was sifting through the heterogeneous QEMU effort in archives here
https://lists.gnu.org/archive/html/qemu-devel/2015-10/msg06256.html
Did this effort make it to the mainline ? Are there any examples of AMP
SoC's in the mainline ?
--
Regards,
Karthik Poduval
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* Re: Heterogeneous/AMP example in mainline?
2020-09-18 13:06 Heterogeneous/AMP example in mainline? karthik poduval
@ 2020-09-18 15:08 ` Peter Maydell
2020-09-18 16:46 ` karthik poduval
0 siblings, 1 reply; 3+ messages in thread
From: Peter Maydell @ 2020-09-18 15:08 UTC (permalink / raw)
To: karthik poduval; +Cc: QEMU Developers
On Fri, 18 Sep 2020 at 14:15, karthik poduval <karthik.poduval@gmail.com> wrote:
> Was sifting through the heterogeneous QEMU effort in archives here
> https://lists.gnu.org/archive/html/qemu-devel/2015-10/msg06256.html
>
> Did this effort make it to the mainline ? Are there any examples of
> AMP SoC's in the mainline ?
In upstream we can handle having asymmetric configurations
as long as all the CPUs are the same basic architecture:
so you can have for instance an Arm Cortex-M and a Cortex-A
in the same board model (there's a xilinx board model
with a mix of cortex-a53 and cortex-r5 cores in the tree).
But we can't handle having multiple different architectures (eg
Arm and x86) in the same board at once. It would be nice to be
able to do that, but it would require a lot of untangling of
things which currently assume various parameters that are
guest-architecture-specific are compile-time fixed things.
So far nobody has been sufficiently interested in having
asymmetric configs to put in that work.
thanks
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Heterogeneous/AMP example in mainline?
2020-09-18 15:08 ` Peter Maydell
@ 2020-09-18 16:46 ` karthik poduval
0 siblings, 0 replies; 3+ messages in thread
From: karthik poduval @ 2020-09-18 16:46 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
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Thanks Peter,
I will go through the Xilinx example.
--
Regards,
Karthik Poduval
On Fri, Sep 18, 2020 at 8:08 AM Peter Maydell <peter.maydell@linaro.org>
wrote:
> On Fri, 18 Sep 2020 at 14:15, karthik poduval <karthik.poduval@gmail.com>
> wrote:
> > Was sifting through the heterogeneous QEMU effort in archives here
> > https://lists.gnu.org/archive/html/qemu-devel/2015-10/msg06256.html
> >
> > Did this effort make it to the mainline ? Are there any examples of
> > AMP SoC's in the mainline ?
>
> In upstream we can handle having asymmetric configurations
> as long as all the CPUs are the same basic architecture:
> so you can have for instance an Arm Cortex-M and a Cortex-A
> in the same board model (there's a xilinx board model
> with a mix of cortex-a53 and cortex-r5 cores in the tree).
> But we can't handle having multiple different architectures (eg
> Arm and x86) in the same board at once. It would be nice to be
> able to do that, but it would require a lot of untangling of
> things which currently assume various parameters that are
> guest-architecture-specific are compile-time fixed things.
> So far nobody has been sufficiently interested in having
> asymmetric configs to put in that work.
>
> thanks
> -- PMM
>
--
Regards,
Karthik Poduval
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