From: Alexey Baturo <baturo.alexey@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Deepak Gupta <debug@rivosinc.com>,
zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com,
Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu,
kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org,
qemu-riscv@nongnu.org
Subject: Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
Date: Sun, 21 Jan 2024 10:13:54 +0300 [thread overview]
Message-ID: <CAFukJ-Cf51kS17BOCkuPpxGXS+h4-MENKqBH5EW7Bj0mz+KPRQ@mail.gmail.com> (raw)
In-Reply-To: <5b6571d3-f654-488d-9dc5-0d18ba542e05@linaro.org>
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Hi,
Having the feature to run binaries with pointer masking on qemu-user is
really nice, but I see this patch series as an initial support.
Obviously there'll be more patches and fixes for pointer masking as soon as
arch tests are ready.
I suggest supporting qemu-user in the next patches, but make sure we do
this before claiming 100% support for pointer masking.
@Deepak Gupta <debug@rivosinc.com> what do you think?
Thanks
сб, 20 янв. 2024 г. в 10:37, Richard Henderson <richard.henderson@linaro.org
>:
> On 1/19/24 09:40, Deepak Gupta wrote:
> > On Thu, Jan 18, 2024 at 12:50 PM Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >> At some point pointer masking will be in hardware, and the kernel will
> gain support for
> >> it, and there will likely be a prctl() added for it. At the point the
> kernel finalizes
> >> the API, you will be able to enable pointer masking for qemu-user.
> >
> > I am sure I am missing some important detail here, BUT...
> >
> > How is it different from aarch64 "top byte ignore".
>
> It is very similar, yes.
>
> > I think commit: 16c8497 enables top byte ignore for user pointers and
> > by default for qemu-user for aarch64 target.
>
> Not quite, no.
>
> commit 0e0c030c681730f3ec55ba3b223b608a8f3e8282
> Author: Richard Henderson <richard.henderson@linaro.org>
> Date: Fri Feb 12 10:48:51 2021 -0800
>
> linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE
>
> is more relevant.
>
> > IIRC, user <--> kernel abi is only needed for pointers that are passed
> > to the kernel.
>
> It is also needed to *enable* pointer masking at all.
>
> For aarch64, TBI has been enabled for user-space since the beginning, but
> that is not true
> for riscv. Therefore there will be a need for a syscall to opt in and
> enable pointer masking.
>
> > And in the case of qemu-user, we are talking about the host kernel.
>
> No, we are not. We are always emulating the guest kernel.
>
>
> r~
>
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next prev parent reply other threads:[~2024-01-21 7:14 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-09 10:29 [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
2024-01-09 10:29 ` [PATCH v4 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
2024-01-22 6:53 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
2024-01-22 7:04 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
2024-01-18 17:21 ` Deepak Gupta
2024-01-18 20:50 ` Richard Henderson
2024-01-18 22:40 ` Deepak Gupta
2024-01-20 7:37 ` Richard Henderson
2024-01-21 7:13 ` Alexey Baturo [this message]
2024-01-23 17:44 ` Deepak Gupta
2024-01-09 10:29 ` [PATCH v4 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
2024-01-22 7:01 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
2024-01-22 7:01 ` Alistair Francis
2024-01-09 10:29 ` [PATCH v4 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
2024-01-22 6:54 ` Alistair Francis
2024-01-22 6:52 ` [PATCH v4 0/6] Pointer Masking update for Zjpm v0.8 Alistair Francis
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