From: Alexey Baturo <baturo.alexey@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Bin Meng <bin.meng@windriver.com>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"space.monkey.delivers@gmail.com"
<space.monkey.delivers@gmail.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Dave Smith <kupokupokupopo@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v13 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension
Date: Sun, 17 Oct 2021 20:14:20 +0300 [thread overview]
Message-ID: <CAFukJ-DQncmtYiDGo9nLP9NCL-QmQU_fBZbW-QWrAAnPnPspYA@mail.gmail.com> (raw)
In-Reply-To: <c66f7198-362e-8311-b063-e88b018044b1@linaro.org>
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Hi Richard,
Thanks for the review.
>Merge error.
fixed
>You might as well place the function correctly in the previous patch.
>Drop the silly alignment of parameters.
fixed
> int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
fixed
>priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
fixed
сб, 16 окт. 2021 г. в 03:01, Richard Henderson <richard.henderson@linaro.org
>:
> On 10/15/21 12:29 PM, Alexey Baturo wrote:
> > FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
> > +/* If PointerMasking should be applied */
> > +FIELD(TB_FLAGS, PM_ENABLED, 10, 1)
>
> Merge error.
>
> > + if (riscv_has_ext(env, RVJ)) {
> > + int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK;
>
> cpu_mmu_index has already been computed.
> You want
>
> int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
>
> > @@ -118,16 +125,6 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> > tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
> > }
> >
> > -/*
> > - * Temp stub: generates address adjustment for PointerMasking
> > - */
> > -static void gen_pm_adjust_address(DisasContext *s,
> > - TCGv *dst,
> > - TCGv src)
> > -{
> > - tcg_gen_mov_tl(*dst, src);
> > -}
> > -
>
> You might as well place the function correctly in the previous patch.
> Drop the silly alignment of parameters.
>
> > + int priv = cpu_mmu_index(env, false) & TB_FLAGS_PRIV_MMU_MASK;
> > + ctx->pm_mask = pm_mask[priv];
>
> Using cpu_mmu_index within the translator is incorrect. You want
>
> priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
>
>
> r~
>
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next prev parent reply other threads:[~2021-10-17 17:16 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-15 19:29 [PATCH v13 0/7] RISC-V Pointer Masking implementatio Alexey Baturo
2021-10-15 19:29 ` [PATCH v13 1/7] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2021-10-15 19:29 ` [PATCH v13 2/7] [RISCV_PM] Add CSR defines for RISC-V PM extension Alexey Baturo
2021-10-15 19:29 ` [PATCH v13 3/7] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo
2021-10-16 0:03 ` Richard Henderson
2021-10-15 19:29 ` [PATCH v13 4/7] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2021-10-15 19:29 ` [PATCH v13 5/7] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2021-10-15 23:49 ` Richard Henderson
2021-10-17 17:21 ` Alexey Baturo
2021-10-15 19:29 ` [PATCH v13 6/7] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2021-10-16 0:01 ` Richard Henderson
2021-10-17 17:14 ` Alexey Baturo [this message]
2021-10-15 19:29 ` [PATCH v13 7/7] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo
2021-10-16 0:04 ` Richard Henderson
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