From: Jim Wilson <jimw@sifive.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
"Jonathan Behrens" <jonathan@fintelia.io>,
"Palmer Dabbelt" <palmer@sifive.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: Re: [PATCH v2] target/riscv: Expose "priv" register for GDB
Date: Tue, 8 Oct 2019 09:42:44 -0700 [thread overview]
Message-ID: <CAFyWVaZUhmqQWvEvPpbYV2dKdf-GB1Dp1mFR5C3JYd221q12GA@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmXXwZTu2rJ7Oen4mVSBjp+-7Jd7WBpmds1xm9m-tR+Q-A@mail.gmail.com>
On Tue, Oct 8, 2019 at 2:00 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> My gdb does not list "priv" register after applying this patch.
I didn't try the patch, I didn't have time for that. I would expect
priv to be in the "info registers" output if you are adding it to the
cpu register set. Shrug. Anyways, defining priv as a virtual
register is the right way to do this, as it isn't a cpu register, and
gdb already has support for virtual registers like priv.
Jim
prev parent reply other threads:[~2019-10-08 16:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-04 15:16 [PATCH v2] target/riscv: Expose "priv" register for GDB Jonathan Behrens
2019-10-05 12:08 ` Bin Meng
2019-10-07 18:31 ` Alistair Francis
2019-10-08 0:22 ` Jonathan Behrens
2019-10-07 21:16 ` Jim Wilson
2019-10-08 0:19 ` Jonathan Behrens
2019-10-08 9:00 ` Bin Meng
2019-10-08 16:42 ` Jim Wilson [this message]
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