From: Jim Wilson <jimw@sifive.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
wxy194768@alibaba-inc.com,
Chih-Min Chao <chihmin.chao@sifive.com>,
wenmeng_zhang@c-sky.com, Palmer Dabbelt <palmer@dabbelt.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v5 0/4] target-riscv: support vector extension part 1
Date: Wed, 26 Feb 2020 15:39:52 -0800 [thread overview]
Message-ID: <CAFyWVabLp78M2RGe0TDF5TyW4sJpa6Rm0sJLnc3-CPv8pW+TzA@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKOedrW3HZFfep4ErJ8H86V=KXeBL8LN2Cy_+669a6c9gQ@mail.gmail.com>
On Wed, Feb 26, 2020 at 2:36 PM Alistair Francis <alistair23@gmail.com> wrote:
> On Wed, Feb 26, 2020 at 12:09 PM Jim Wilson <jimw@sifive.com> wrote:
> > If this rvv 0.7.1 implementation is considered a temporary solution,
> > maybe we can just remove all of this work when the official rvv spec if
> > available? But presumably it is better if we can have both this
>
> That is generally the plan. When the final spec comes out this will be
> updated and we will only support that.
This solves my problem, but maybe creates one for Alibaba. They have
apparently fabbed a chip using the 0.7.1 draft of the vector spec
proposal. So for qemu to properly support their asic, the 0.7.1 draft
support will have to be retained. But I think SiFive and everyone
else is waiting for the official spec before building asics with
vector support. If Alibaba will update their processor as the spec
evolves, then maybe this isn't a problem for them.
Jim
next prev parent reply other threads:[~2020-02-26 23:40 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-21 9:45 [PATCH v5 0/4] target-riscv: support vector extension part 1 LIU Zhiwei
2020-02-21 9:45 ` [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-02-26 18:03 ` Alistair Francis
2020-02-27 20:32 ` Richard Henderson
2020-02-21 9:45 ` [PATCH v5 2/4] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-02-26 18:05 ` Alistair Francis
2020-02-27 20:33 ` Richard Henderson
2020-02-21 9:45 ` [PATCH v5 3/4] target/riscv: support vector extension csr LIU Zhiwei
2020-02-26 18:42 ` Alistair Francis
2020-02-27 0:41 ` LIU Zhiwei
2020-02-26 20:16 ` Jim Wilson
2020-02-21 9:45 ` [PATCH v5 4/4] target/riscv: add vector configure instruction LIU Zhiwei
2020-02-26 19:20 ` Alistair Francis
2020-02-27 1:41 ` LIU Zhiwei
2020-02-27 21:48 ` Alistair Francis
2020-02-26 20:20 ` Jim Wilson
2020-02-26 20:09 ` [PATCH v5 0/4] target-riscv: support vector extension part 1 Jim Wilson
2020-02-26 22:28 ` Alistair Francis
2020-02-26 23:39 ` Jim Wilson [this message]
2020-02-26 23:46 ` Alistair Francis
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