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bh=NV+OZMs6D87G1r9TAbScVDoH7fAKIH759q80yM8yV0I=; b=iIGZxXqpZUblGRJ8dmsGi2tPpelpycWFAu/1XL/pQmZ25+p+GLIgFaT8dsfqUFpuK9 8hReaQKZMQht10C7Wa8ge49k5mbi9IajsnITGXPouBRbeAcYgLqFl/tyhMHIO9L9hACT YUB6pPgj+SSOr5TKMyqfPPBFR1EcQbHKWf6NeKmyEno7IKFz4FfGfQmAZ4VStgffr+5G U1LYr/jMIHbet/4q9JEmS9EsCuIjYc+/TPCZkU3ZW/HWKrpeWcBF9n1XXVlbnF4rr+tl 6gnj31PArH5h6xVSVdHwSD1yS2O9XrCLKcb5LJDVMy0vi9bWeM1xeIlzJ3T7vinYpprX rSbQ== X-Gm-Message-State: AC+VfDwW7WrvHM0dr6ehlMQIbrLo42qXGVKvh8NXd/cQYO43NNeys9At sCWTd41WQfLxRVi2ZEEAP6elKqoSRRUU0cOz/cIQL21QYfLQoiP3rK0= X-Google-Smtp-Source: ACHHUZ5aySdyvCSaWy7KHe8kX6c+uWcaxxh6XI7QfluJt7LlVobJidfPqLwdFCF3VkqkPXt0ns2Q/TVfZwYB6Xz7P4U= X-Received: by 2002:a17:902:be14:b0:1b1:b111:dfe8 with SMTP id r20-20020a170902be1400b001b1b111dfe8mr3062734pls.66.1686080815794; Tue, 06 Jun 2023 12:46:55 -0700 (PDT) MIME-Version: 1.0 References: <20230606113812.519723-1-hchauhan@ventanamicro.com> In-Reply-To: <20230606113812.519723-1-hchauhan@ventanamicro.com> From: =?UTF-8?B?TG/Dr2MgTGVmb3J0?= Date: Tue, 6 Jun 2023 21:46:45 +0200 Message-ID: Subject: Re: [PATCH] Add epmp to extensions list and rename it to smepmp To: Himanshu Chauhan Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=loic@rivosinc.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Jun 6, 2023 at 1:39=E2=80=AFPM Himanshu Chauhan wrote: > > Smepmp is a ratified extension which qemu refers to as epmp. > Rename epmp to smepmp and add it to extension list so that > it is added to the isa string. > > Signed-off-by: Himanshu Chauhan > --- > target/riscv/cpu.c | 9 +++++---- > target/riscv/cpu_cfg.h | 2 +- > target/riscv/csr.c | 6 +++--- > target/riscv/pmp.c | 12 ++++++------ > 4 files changed, 15 insertions(+), 14 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 881bddf393..cf3d1c3207 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -127,6 +127,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), > @@ -547,7 +548,7 @@ static void rv32_ibex_cpu_init(Object *obj) > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > #endif > - cpu->cfg.epmp =3D true; > + cpu->cfg.ext_smepmp =3D true; > Should also update Ibex CPU to priv level 1.12 otherwise Smepmp will be disabled since it is now declared PRIV_VERSION_1_12_0 in isa_edata_arr. > /* inherited from parent obj via riscv_cpu_init() */ > cpu->cfg.ext_ifencei =3D true; > @@ -1336,12 +1337,12 @@ static void riscv_cpu_realize(DeviceState *dev, E= rror **errp) > return; > } > > - if (cpu->cfg.epmp && !cpu->cfg.pmp) { > + if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { > /* > * Enhanced PMP should only be available > * on harts with PMP support > */ > - error_setg(errp, "Invalid configuration: EPMP requires PMP suppo= rt"); > + error_setg(errp, "Invalid configuration: SMEPMP requires PMP sup= port"); > return; > } Nitpick: the spec uses "Smepmp", not "SMEPMP". > > @@ -1676,7 +1677,7 @@ static Property riscv_cpu_extensions[] =3D { > DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), > > /* ePMP 0.9.3 */ > - DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > + DEFINE_PROP_BOOL("smepmp", RISCVCPU, cfg.ext_smepmp, false), > DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), > DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), > You missed the comment update but maybe just move the definition next to pmp and drop the comment since it's now ratified? > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index c4a627d335..d79b022e35 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -87,6 +87,7 @@ struct RISCVCPUConfig { > bool ext_zvfh; > bool ext_zvfhmin; > bool ext_smaia; > + bool ext_smepmp; > bool ext_ssaia; > bool ext_sscofpmf; > bool rvv_ta_all_1s; > @@ -121,7 +122,6 @@ struct RISCVCPUConfig { > uint16_t cboz_blocksize; > bool mmu; > bool pmp; > - bool epmp; > bool debug; > bool misa_w; > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 58499b5afc..d9bc591348 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -523,9 +523,9 @@ static RISCVException pmp(CPURISCVState *env, int csr= no) > return RISCV_EXCP_ILLEGAL_INST; > } > > -static RISCVException epmp(CPURISCVState *env, int csrno) > +static RISCVException smepmp(CPURISCVState *env, int csrno) > { > - if (riscv_cpu_cfg(env)->epmp) { > + if (riscv_cpu_cfg(env)->ext_smepmp) { > return RISCV_EXCP_NONE; > } > > @@ -4356,7 +4356,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { > [CSR_VSIPH] =3D { "vsiph", aia_hmode32, NULL, NULL, rmw_= vsiph }, > > /* Physical Memory Protection */ > - [CSR_MSECCFG] =3D { "mseccfg", epmp, read_mseccfg, write_mseccfg= , > + [CSR_MSECCFG] =3D { "mseccfg", smepmp, read_mseccfg, write_mseccf= g, > .min_priv_ver =3D PRIV_VERSION_1_11_0 = }, > [CSR_PMPCFG0] =3D { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg = }, > [CSR_PMPCFG1] =3D { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg = }, > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index 418738afd8..18246e1737 100644 > --- a/target/riscv/pmp.c > +++ b/target/riscv/pmp.c > @@ -87,7 +87,7 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t = pmp_index, uint8_t val) > if (pmp_index < MAX_RISCV_PMPS) { > bool locked =3D true; > > - if (riscv_cpu_cfg(env)->epmp) { > + if (riscv_cpu_cfg(env)->ext_smepmp) { > /* mseccfg.RLB is set */ > if (MSECCFG_RLB_ISSET(env)) { > locked =3D false; > @@ -337,9 +337,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ul= ong addr, > > /* > * Convert the PMP permissions to match the truth table in the > - * ePMP spec. > + * SMEPMP spec. > */ Smepmp > - const uint8_t epmp_operation =3D > + const uint8_t smepmp_operation =3D > ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) | > ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) | > (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) | > @@ -364,7 +364,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ul= ong addr, > * If mseccfg.MML Bit set, do the enhanced pmp priv chec= k > */ > if (mode =3D=3D PRV_M) { > - switch (epmp_operation) { > + switch (smepmp_operation) { > case 0: > case 1: > case 4: > @@ -395,7 +395,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ul= ong addr, > g_assert_not_reached(); > } > } else { > - switch (epmp_operation) { > + switch (smepmp_operation) { > case 0: > case 8: > case 9: > @@ -576,7 +576,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulo= ng val) > } > } > > - if (riscv_cpu_cfg(env)->epmp) { > + if (riscv_cpu_cfg(env)->ext_smepmp) { > /* Sticky bits */ > val |=3D (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML)); > if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) { > -- > 2.34.1 > >