From: Hao Wu <wuhaotsh@google.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>,
IS20 Avi Fishman <Avi.Fishman@nuvoton.com>,
CS20 KFTing <kfting@nuvoton.com>,
Havard Skinnemoen <hskinnemoen@google.com>,
Patrick Venture <venture@google.com>, Doug Evans <dje@google.com>,
Corey Minyard <cminyard@mvista.com>
Subject: Re: [PATCH v2 6/6] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode
Date: Wed, 10 Feb 2021 13:42:48 -0800 [thread overview]
Message-ID: <CAGcCb11eUrZhRZy4aT=t9078RF81kBSLTROF9gk8-me0nL4euw@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA-8q2DZpdbeiMhrxtAMkzx1_1BqcGTk8HfxX_6F_FOUfQ@mail.gmail.com>
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On Mon, Feb 8, 2021 at 8:59 AM Peter Maydell <peter.maydell@linaro.org>
wrote:
> On Fri, 29 Jan 2021 at 01:04, Hao Wu <wuhaotsh@google.com> wrote:
> >
> > This patch implements the FIFO mode of the SMBus module. In FIFO, the
> > user transmits or receives at most 16 bytes at a time. The FIFO mode
> > allows the module to transmit large amount of data faster than single
> > byte mode.
> >
> > Reviewed-by: Doug Evans<dje@google.com>
> > Reviewed-by: Tyrong Ting<kfting@nuvoton.com>
> > Signed-off-by: Hao Wu <wuhaotsh@google.com>
> > Reviewed-by: Corey Minyard <cminyard@mvista.com>
> > Ack-by: Corey Minyard <cminyard@mvista.com>
> > ---
> > hw/i2c/npcm7xx_smbus.c | 342 +++++++++++++++++++++++++++++--
> > hw/i2c/trace-events | 1 +
> > include/hw/i2c/npcm7xx_smbus.h | 25 +++
> > tests/qtest/npcm7xx_smbus-test.c | 149 +++++++++++++-
> > 4 files changed, 501 insertions(+), 16 deletions(-)
> >
> > diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c
> > index c72b6e446f..be3253d251 100644
> > --- a/hw/i2c/npcm7xx_smbus.c
> > +++ b/hw/i2c/npcm7xx_smbus.c
> > @@ -27,7 +27,7 @@
> > #include "trace.h"
> >
> > #define NPCM7XX_SMBUS_VERSION 1
> > -#define NPCM7XX_SMBUS_FIFO_EN 0
> > +#define NPCM7XX_SMBUS_FIFO_EN 1
>
> Why has this define changed ?
>
> > #define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE)
> > +#define NPCM7XX_SMBUS_FIFO_ENABLED(s) (NPCM7XX_SMBUS_FIFO_EN && \
> > + (s)->fif_ctl & NPCM7XX_SMBFIF_CTL_FIFO_EN)
>
> ...and why are we testing something that's always 1 ?
> Is NPCM7XX_SMBUS_FIFO_EN supposed to be a debug "turn this feature off"
> switch for QEMU developers? If, so it would be helpful to give it a name
> that doesn't look like it's defining a bit value for the hardware
> and adding a comment saying what it does.
>
No, it's a specific bit in the NPCM7XX SMBus module's version reg that
indicates whether this module
supports FIFO mode. I'll rename it so it's more clear to the reader.
>
> > @@ -754,6 +1059,17 @@ static const VMStateDescription
> vmstate_npcm7xx_smbus = {
> > VMSTATE_UINT8_ARRAY(addr, NPCM7xxSMBusState,
> NPCM7XX_SMBUS_NR_ADDRS),
> > VMSTATE_UINT8(scllt, NPCM7xxSMBusState),
> > VMSTATE_UINT8(sclht, NPCM7xxSMBusState),
> > + VMSTATE_UINT8(fif_ctl, NPCM7xxSMBusState),
> > + VMSTATE_UINT8(fif_cts, NPCM7xxSMBusState),
> > + VMSTATE_UINT8(fair_per, NPCM7xxSMBusState),
> > + VMSTATE_UINT8(txf_ctl, NPCM7xxSMBusState),
> > + VMSTATE_UINT8(t_out, NPCM7xxSMBusState),
> > + VMSTATE_UINT8(txf_sts, NPCM7xxSMBusState),
> > + VMSTATE_UINT8(rxf_sts, NPCM7xxSMBusState),
> > + VMSTATE_UINT8(rxf_ctl, NPCM7xxSMBusState),
> > + VMSTATE_UINT8_ARRAY(rx_fifo, NPCM7xxSMBusState,
> > + NPCM7XX_SMBUS_FIFO_SIZE),
> > + VMSTATE_UINT8(rx_cur, NPCM7xxSMBusState),
> > VMSTATE_END_OF_LIST(),
> > },
> > };
>
> It's OK to add fields to the vmstate without bumping the version
> number in this special case, because we only just added the device
> a few commits earlier in the series, but it's worth specifically
> saying that in the commit message.
>
> thanks
> -- PMM
>
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next prev parent reply other threads:[~2021-02-10 21:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-29 0:58 [PATCH v2 0/6] hw/i2c: Add NPCM7XX SMBus Device wuhaotsh--- via
2021-01-29 0:58 ` [PATCH v2 1/6] hw/arm: Remove GPIO from unimplemented NPCM7XX wuhaotsh--- via
2021-02-08 16:48 ` Peter Maydell
2021-01-29 0:58 ` [PATCH v2 2/6] hw/i2c: Implement NPCM7XX SMBus Module Single Mode wuhaotsh--- via
2021-01-29 0:58 ` [PATCH v2 3/6] hw/arm: Add I2C sensors for NPCM750 eval board wuhaotsh--- via
2021-02-08 16:48 ` Peter Maydell
2021-01-29 0:58 ` [PATCH v2 4/6] hw/arm: Add I2C sensors and EEPROM for GSJ machine wuhaotsh--- via
2021-02-08 16:51 ` Peter Maydell
2021-01-29 0:58 ` [PATCH v2 5/6] hw/i2c: Add a QTest for NPCM7XX SMBus Device wuhaotsh--- via
2021-02-08 16:51 ` Peter Maydell
2021-01-29 0:58 ` [PATCH v2 6/6] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode wuhaotsh--- via
2021-02-08 16:59 ` Peter Maydell
2021-02-10 21:42 ` Hao Wu [this message]
2021-02-08 17:01 ` [PATCH v2 0/6] hw/i2c: Add NPCM7XX SMBus Device Peter Maydell
2021-02-10 21:26 ` Hao Wu
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