From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53DE8C4361B for ; Tue, 15 Dec 2020 00:28:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C1E1022210 for ; Tue, 15 Dec 2020 00:28:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C1E1022210 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=nongnu.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:38438 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1koyCv-0006Sq-IU for qemu-devel@archiver.kernel.org; Mon, 14 Dec 2020 19:28:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47394) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1koy1P-0004XY-Hu for qemu-devel@nongnu.org; Mon, 14 Dec 2020 19:17:00 -0500 Received: from mail-lf1-x143.google.com ([2a00:1450:4864:20::143]:46966) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1koy1K-0003WT-KO for qemu-devel@nongnu.org; Mon, 14 Dec 2020 19:16:55 -0500 Received: by mail-lf1-x143.google.com with SMTP id y19so34789244lfa.13 for ; Mon, 14 Dec 2020 16:16:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=KUClhekkUfnVtYs4hq8OfWJQ89NHr94pk2v0JJC2WQI=; b=S5vSUMoVND0ojHnpHbW6YxfgMYuv3Fi5x97oHwpR1ZHnlMZNz2q8yCZiOTr9yZoVpx DHDeKKGtEopp5E1I9EqvUbZRU+efsE+4aTg3/hgoGC+YgbknRRD/OqdKMVf17Z6p9gG3 yzsEmKQqKJNW9VJrCkzsYe3oQmQmeyWU45L4+TS0KhlwxbpbShBcQ3azAgXO2o02lCVG OVnDokIvVhpYIzQ5EqbVKD6qFcZ/We62V/VcmvHuG2P2NkGjmWhkUo/7AidmAStR1FAy Sx3X9kOj3Vgu8vsr9hSzFlMdSUcmvJjdlACBubUq7yZsfoDadULJzBixiBHxyiXMoX8C EYBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=KUClhekkUfnVtYs4hq8OfWJQ89NHr94pk2v0JJC2WQI=; b=CEsHuOIXHHbW1lKLNRZNwOVH18WTJLBwpeJPopX+jT7c4j4xCBNb5Ykcy0n/UJO18S 61AucyybQ35kbgI+2B3NQMpaifj0sHcCNqsrgIwmjt1rXT1E3vBDXshkkuuuPIa9Orqo DvVUu1f94n5PerOY7lmtRnsMBWlvID7UF3ouIxY51Bpl8/pNbgzUa7RWawuW9n4fYdf4 T5u+fmsAko+UkrW1i7ODptCFb0lsocUOFiVseKQTdVNuAjjAGdDYcVlnKQ6jx7jhRDIP hAwlLy0O9uxI5xpPmchE3GObM71BZhPO/Hq430xmjL8T3Y9aHOpZ7HpG9LIExm2uCdll 7/og== X-Gm-Message-State: AOAM530zyW5JRr7y46lFMmT/gdarho/2kq32Al4iz3k/E852JVtw2hOo YwzIe+jD1Z1IBKOCgjtp1rZo2G0hzPL8w83lWynm2CFcCORKVQ== X-Google-Smtp-Source: ABdhPJwrpkzigSSxKAorClYjq0HB/Uo93rCmSLuzZCOJLWtPSi1MQHsO8De3nCutBO7374fdh0JZucDfKhVgx+SItTM= X-Received: by 2002:a2e:8745:: with SMTP id q5mr11016593ljj.77.1607991408970; Mon, 14 Dec 2020 16:16:48 -0800 (PST) MIME-Version: 1.0 References: <20201215001312.3120777-1-wuhaotsh@google.com> <20201215001312.3120777-3-wuhaotsh@google.com> In-Reply-To: <20201215001312.3120777-3-wuhaotsh@google.com> Date: Mon, 14 Dec 2020 16:16:36 -0800 Message-ID: Subject: Re: [PATCH v3 2/5] hw/timer: Refactor NPCM7XX Timer to use CLK clock To: Peter Maydell Content-Type: multipart/alternative; boundary="000000000000bc309505b675ac34" Received-SPF: pass client-ip=2a00:1450:4864:20::143; envelope-from=wuhaotsh@google.com; helo=mail-lf1-x143.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: minyard@acm.org, Patrick Venture , Havard Skinnemoen , QEMU Developers , CS20 KFTing , qemu-arm , IS20 Avi Fishman , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Hao Wu From: Hao Wu via --000000000000bc309505b675ac34 Content-Type: text/plain; charset="UTF-8" On Mon, Dec 14, 2020 at 4:13 PM Hao Wu wrote: > This patch makes NPCM7XX Timer to use a the timer clock generated by the > CLK module instead of the magic number TIMER_REF_HZ. > > Reviewed-by: Havard Skinnemoen > Reviewed-by: Tyrone Ting > Signed-off-by: Hao Wu > --- > hw/arm/npcm7xx.c | 5 +++++ > hw/timer/npcm7xx_timer.c | 23 +++++++++++++---------- > include/hw/misc/npcm7xx_clk.h | 6 ------ > include/hw/timer/npcm7xx_timer.h | 1 + > 4 files changed, 19 insertions(+), 16 deletions(-) > > diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c > index 47e2b6fc40..fabfb1697b 100644 > --- a/hw/arm/npcm7xx.c > +++ b/hw/arm/npcm7xx.c > @@ -22,6 +22,7 @@ > #include "hw/char/serial.h" > #include "hw/loader.h" > #include "hw/misc/unimp.h" > +#include "hw/qdev-clock.h" > #include "hw/qdev-properties.h" > #include "qapi/error.h" > #include "qemu/units.h" > @@ -420,6 +421,10 @@ static void npcm7xx_realize(DeviceState *dev, Error > **errp) > int first_irq; > int j; > > + /* Connect the timer clock. */ > + qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", > qdev_get_clock_out( > + DEVICE(&s->clk), "timer-clock")); > + > sysbus_realize(sbd, &error_abort); > sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); > > diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c > index d24445bd6e..8147b53000 100644 > --- a/hw/timer/npcm7xx_timer.c > +++ b/hw/timer/npcm7xx_timer.c > @@ -17,8 +17,8 @@ > #include "qemu/osdep.h" > > #include "hw/irq.h" > +#include "hw/qdev-clock.h" > #include "hw/qdev-properties.h" > -#include "hw/misc/npcm7xx_clk.h" > #include "hw/timer/npcm7xx_timer.h" > #include "migration/vmstate.h" > #include "qemu/bitops.h" > @@ -130,7 +130,7 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer > *t, uint32_t count) > { > int64_t ns = count; > > - ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ; > + ns *= clock_get_ns(t->ctrl->clock); > ns *= npcm7xx_tcsr_prescaler(t->tcsr); > > return ns; > @@ -141,7 +141,7 @@ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer > *t, int64_t ns) > { > int64_t count; > > - count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ); > + count = ns / clock_get_ns(t->ctrl->clock); > count /= npcm7xx_tcsr_prescaler(t->tcsr); > > return count; > @@ -167,7 +167,7 @@ static void > npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, > int64_t cycles) > { > uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t); > - int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles; > + int64_t ns = clock_get_ns(t->ctrl->clock) * cycles; > > /* > * The reset function always clears the current timer. The caller of > the > @@ -606,10 +606,11 @@ static void npcm7xx_timer_hold_reset(Object *obj) > qemu_irq_lower(s->watchdog_timer.irq); > } > > -static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) > +static void npcm7xx_timer_init(Object *obj) > { > - NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev); > + NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); > SysBusDevice *sbd = &s->parent; > + DeviceState *dev = DEVICE(obj); > int i; > NPCM7xxWatchdogTimer *w; > > @@ -627,11 +628,12 @@ static void npcm7xx_timer_realize(DeviceState *dev, > Error **errp) > npcm7xx_watchdog_timer_expired, w); > sysbus_init_irq(sbd, &w->irq); > > - memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s, > + memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s, > TYPE_NPCM7XX_TIMER, 4 * KiB); > sysbus_init_mmio(sbd, &s->iomem); > qdev_init_gpio_out_named(dev, &w->reset_signal, > NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); > + s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL); > } > > static const VMStateDescription vmstate_npcm7xx_base_timer = { > @@ -675,10 +677,11 @@ static const VMStateDescription > vmstate_npcm7xx_watchdog_timer = { > > static const VMStateDescription vmstate_npcm7xx_timer_ctrl = { > .name = "npcm7xx-timer-ctrl", > - .version_id = 1, > - .minimum_version_id = 1, > + .version_id = 2, > + .minimum_version_id = 2, > .fields = (VMStateField[]) { > VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState), > + VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState), > VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState, > NPCM7XX_TIMERS_PER_CTRL, 0, > vmstate_npcm7xx_timer, > NPCM7xxTimer), > @@ -697,7 +700,6 @@ static void npcm7xx_timer_class_init(ObjectClass > *klass, void *data) > QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS); > > dc->desc = "NPCM7xx Timer Controller"; > - dc->realize = npcm7xx_timer_realize; > dc->vmsd = &vmstate_npcm7xx_timer_ctrl; > rc->phases.enter = npcm7xx_timer_enter_reset; > rc->phases.hold = npcm7xx_timer_hold_reset; > @@ -708,6 +710,7 @@ static const TypeInfo npcm7xx_timer_info = { > .parent = TYPE_SYS_BUS_DEVICE, > .instance_size = sizeof(NPCM7xxTimerCtrlState), > .class_init = npcm7xx_timer_class_init, > + .instance_init = npcm7xx_timer_init, > }; > > static void npcm7xx_timer_register_type(void) > diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h > index f641f95f3e..d5c8d16ca4 100644 > --- a/include/hw/misc/npcm7xx_clk.h > +++ b/include/hw/misc/npcm7xx_clk.h > @@ -20,12 +20,6 @@ > #include "hw/clock.h" > #include "hw/sysbus.h" > > -/* > - * The reference clock frequency for the timer modules, and the SECCNT and > - * CNTR25M registers in this module, is always 25 MHz. > - */ > -#define NPCM7XX_TIMER_REF_HZ (25000000) > - > /* > * Number of registers in our device state structure. Don't change this > without > * incrementing the version_id in the vmstate. > diff --git a/include/hw/timer/npcm7xx_timer.h > b/include/hw/timer/npcm7xx_timer.h > index 6993fd723a..d45c051b56 100644 > --- a/include/hw/timer/npcm7xx_timer.h > +++ b/include/hw/timer/npcm7xx_timer.h > @@ -101,6 +101,7 @@ struct NPCM7xxTimerCtrlState { > > uint32_t tisr; > > + Clock *clock; > NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL]; > NPCM7xxWatchdogTimer watchdog_timer; > }; > -- > 2.29.2.684.gfbc64c5ab5-goog > > --000000000000bc309505b675ac34 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Mon, Dec 14, 2020 at 4:13 PM Hao Wu <wuhaotsh@google.com> wrote:
This patch makes NPCM7XX Tim= er to use a the timer clock generated by the
CLK module instead of the magic number TIMER_REF_HZ.

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
---
=C2=A0hw/arm/npcm7xx.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0|=C2=A0 5 +++++
=C2=A0hw/timer/npcm7xx_timer.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 23 ++++++= +++++++----------
=C2=A0include/hw/misc/npcm7xx_clk.h=C2=A0 =C2=A0 |=C2=A0 6 ------
=C2=A0include/hw/timer/npcm7xx_timer.h |=C2=A0 1 +
=C2=A04 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 47e2b6fc40..fabfb1697b 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -22,6 +22,7 @@
=C2=A0#include "hw/char/serial.h"
=C2=A0#include "hw/loader.h"
=C2=A0#include "hw/misc/unimp.h"
+#include "hw/qdev-clock.h"
=C2=A0#include "hw/qdev-properties.h"
=C2=A0#include "qapi/error.h"
=C2=A0#include "qemu/units.h"
@@ -420,6 +421,10 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int first_irq;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int j;

+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Connect the timer clock. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 qdev_connect_clock_in(DEVICE(&s->tim[i]= ), "clock", qdev_get_clock_out(
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 DEVI= CE(&s->clk), "timer-clock"));
+
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_realize(sbd, &error_abort); =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[= i]);

diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
index d24445bd6e..8147b53000 100644
--- a/hw/timer/npcm7xx_timer.c
+++ b/hw/timer/npcm7xx_timer.c
@@ -17,8 +17,8 @@
=C2=A0#include "qemu/osdep.h"

=C2=A0#include "hw/irq.h"
+#include "hw/qdev-clock.h"
=C2=A0#include "hw/qdev-properties.h"
-#include "hw/misc/npcm7xx_clk.h"
=C2=A0#include "hw/timer/npcm7xx_timer.h"
=C2=A0#include "migration/vmstate.h"
=C2=A0#include "qemu/bitops.h"
@@ -130,7 +130,7 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *= t, uint32_t count)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0int64_t ns =3D count;

-=C2=A0 =C2=A0 ns *=3D NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
+=C2=A0 =C2=A0 ns *=3D clock_get_ns(t->ctrl->clock);
=C2=A0 =C2=A0 =C2=A0ns *=3D npcm7xx_tcsr_prescaler(t->tcsr);

=C2=A0 =C2=A0 =C2=A0return ns;
@@ -141,7 +141,7 @@ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer = *t, int64_t ns)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0int64_t count;

-=C2=A0 =C2=A0 count =3D ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_H= Z);
+=C2=A0 =C2=A0 count =3D ns / clock_get_ns(t->ctrl->clock);
=C2=A0 =C2=A0 =C2=A0count /=3D npcm7xx_tcsr_prescaler(t->tcsr);

=C2=A0 =C2=A0 =C2=A0return count;
@@ -167,7 +167,7 @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xx= WatchdogTimer *t,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int64_t cycles)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0uint32_t prescaler =3D npcm7xx_watchdog_timer_prescaler= (t);
-=C2=A0 =C2=A0 int64_t ns =3D (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_H= Z) * cycles;
+=C2=A0 =C2=A0 int64_t ns =3D clock_get_ns(t->ctrl->clock) * cycles;<= br>
=C2=A0 =C2=A0 =C2=A0/*
=C2=A0 =C2=A0 =C2=A0 * The reset function always clears the current timer. = The caller of the
@@ -606,10 +606,11 @@ static void npcm7xx_timer_hold_reset(Object *obj)
=C2=A0 =C2=A0 =C2=A0qemu_irq_lower(s->watchdog_timer.irq);
=C2=A0}

-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
+static void npcm7xx_timer_init(Object *obj)
=C2=A0{
-=C2=A0 =C2=A0 NPCM7xxTimerCtrlState *s =3D NPCM7XX_TIMER(dev);
+=C2=A0 =C2=A0 NPCM7xxTimerCtrlState *s =3D NPCM7XX_TIMER(obj);
=C2=A0 =C2=A0 =C2=A0SysBusDevice *sbd =3D &s->parent;
+=C2=A0 =C2=A0 DeviceState *dev =3D DEVICE(obj);
=C2=A0 =C2=A0 =C2=A0int i;
=C2=A0 =C2=A0 =C2=A0NPCM7xxWatchdogTimer *w;

@@ -627,11 +628,12 @@ static void npcm7xx_timer_realize(DeviceState *dev, E= rror **errp)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0npcm7xx_watchdog_timer_expi= red, w);
=C2=A0 =C2=A0 =C2=A0sysbus_init_irq(sbd, &w->irq);

-=C2=A0 =C2=A0 memory_region_init_io(&s->iomem, OBJECT(s), &npcm= 7xx_timer_ops, s,
+=C2=A0 =C2=A0 memory_region_init_io(&s->iomem, obj, &npcm7xx_ti= mer_ops, s,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0TYPE_NPCM7XX_TIMER, 4 * KiB);
=C2=A0 =C2=A0 =C2=A0sysbus_init_mmio(sbd, &s->iomem);
=C2=A0 =C2=A0 =C2=A0qdev_init_gpio_out_named(dev, &w->reset_signal,<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NPCM7XX_WATCHDOG_RESET_GPIO= _OUT, 1);
+=C2=A0 =C2=A0 s->clock =3D qdev_init_clock_in(dev, "clock", N= ULL, NULL);
=C2=A0}

=C2=A0static const VMStateDescription vmstate_npcm7xx_base_timer =3D {
@@ -675,10 +677,11 @@ static const VMStateDescription vmstate_npcm7xx_watch= dog_timer =3D {

=C2=A0static const VMStateDescription vmstate_npcm7xx_timer_ctrl =3D {
=C2=A0 =C2=A0 =C2=A0.name =3D "npcm7xx-timer-ctrl",
-=C2=A0 =C2=A0 .version_id =3D 1,
-=C2=A0 =C2=A0 .minimum_version_id =3D 1,
+=C2=A0 =C2=A0 .version_id =3D 2,
+=C2=A0 =C2=A0 .minimum_version_id =3D 2,
=C2=A0 =C2=A0 =C2=A0.fields =3D (VMStateField[]) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlStat= e),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState), =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerC= trlState,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx= _timer,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NPCM7xxTimer),
@@ -697,7 +700,6 @@ static void npcm7xx_timer_class_init(ObjectClass *klass= , void *data)
=C2=A0 =C2=A0 =C2=A0QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_T= IMER_NR_REGS);

=C2=A0 =C2=A0 =C2=A0dc->desc =3D "NPCM7xx Timer Controller"; -=C2=A0 =C2=A0 dc->realize =3D npcm7xx_timer_realize;
=C2=A0 =C2=A0 =C2=A0dc->vmsd =3D &vmstate_npcm7xx_timer_ctrl;
=C2=A0 =C2=A0 =C2=A0rc->phases.enter =3D npcm7xx_timer_enter_reset;
=C2=A0 =C2=A0 =C2=A0rc->phases.hold =3D npcm7xx_timer_hold_reset;
@@ -708,6 +710,7 @@ static const TypeInfo npcm7xx_timer_info =3D {
=C2=A0 =C2=A0 =C2=A0.parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =3D TYPE_SYS_BUS_DEVICE,
=C2=A0 =C2=A0 =C2=A0.instance_size=C2=A0 =C2=A0 =C2=A0 =3D sizeof(NPCM7xxTi= merCtrlState),
=C2=A0 =C2=A0 =C2=A0.class_init=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D npcm7x= x_timer_class_init,
+=C2=A0 =C2=A0 .instance_init=C2=A0 =C2=A0 =C2=A0 =3D npcm7xx_timer_init, =C2=A0};

=C2=A0static void npcm7xx_timer_register_type(void)
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h<= br> index f641f95f3e..d5c8d16ca4 100644
--- a/include/hw/misc/npcm7xx_clk.h
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -20,12 +20,6 @@
=C2=A0#include "hw/clock.h"
=C2=A0#include "hw/sysbus.h"

-/*
- * The reference clock frequency for the timer modules, and the SECCNT and=
- * CNTR25M registers in this module, is always 25 MHz.
- */
-#define NPCM7XX_TIMER_REF_HZ=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (250= 00000)
-
=C2=A0/*
=C2=A0 * Number of registers in our device state structure. Don't chang= e this without
=C2=A0 * incrementing the version_id in the vmstate.
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_ti= mer.h
index 6993fd723a..d45c051b56 100644
--- a/include/hw/timer/npcm7xx_timer.h
+++ b/include/hw/timer/npcm7xx_timer.h
@@ -101,6 +101,7 @@ struct NPCM7xxTimerCtrlState {

=C2=A0 =C2=A0 =C2=A0uint32_t=C2=A0 =C2=A0 tisr;

+=C2=A0 =C2=A0 Clock=C2=A0 =C2=A0 =C2=A0 =C2=A0*clock;
=C2=A0 =C2=A0 =C2=A0NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
=C2=A0 =C2=A0 =C2=A0NPCM7xxWatchdogTimer watchdog_timer;
=C2=A0};
--
2.29.2.684.gfbc64c5ab5-goog

--000000000000bc309505b675ac34--