From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, HTML_MESSAGE,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_IN_DEF_DKIM_WL autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 411D0C433E0 for ; Wed, 13 Jan 2021 17:27:06 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8C16920739 for ; Wed, 13 Jan 2021 17:27:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8C16920739 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:38168 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kzjvE-000160-3w for qemu-devel@archiver.kernel.org; Wed, 13 Jan 2021 12:27:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39368) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kzjiO-0005YM-Kc for qemu-devel@nongnu.org; Wed, 13 Jan 2021 12:13:48 -0500 Received: from mail-lf1-x131.google.com ([2a00:1450:4864:20::131]:34980) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kzjiM-0001uI-Km for qemu-devel@nongnu.org; Wed, 13 Jan 2021 12:13:48 -0500 Received: by mail-lf1-x131.google.com with SMTP id u25so3887797lfc.2 for ; Wed, 13 Jan 2021 09:13:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=4F+d8U7HRo/P6Q8u9Ze8a9ylX0+mtB4RwQkuh2io3Zc=; b=fwvxNGVUlUDLuFJPhnmi1C0vcsLfCelIdy7LW3GeLRoOtYDFbMGdb9ajPUiIN29QR2 nts23tYeODo710UEZ4bkovdyfqLeoUO1yGlDgSSQull2QNoZALTcsRTE7+2rJ2apq9rO K+EtdNFpMQSow5ncqFssaYqavSNf1nKUb4GLRTPX6FpgPJWu5EqRQ80U23yY0O0MsPUr 2M1FfAegi1AnNbTViBqRXcXD8pIPXKSeEzAU/SJdI5K6uOtpcoewTeXXU1AKyzPqALUi krwkW9EVx6bKuqB37N6gj5SWZf5T/YrtbS4yvWfZru/xrVVb8Z1H/ti6XZv0r1/F9YfE 9mkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=4F+d8U7HRo/P6Q8u9Ze8a9ylX0+mtB4RwQkuh2io3Zc=; b=ZPxNoJ4eES21y9/PxpVmbjEbHE8erBEujgGZeO7SCvuOUtVqsFupuFYeZFPT0Xy5IV 8Get1VpbmXmsCeM2Xtl2lGSboyg8h85Cr2OIKbDv/qdeYZRs65H3lLN9ofjF+VEQL1as Kys4FfTvLKUdiUQQ0X61QUk1PbY8akdrAMoMWQM4oN5xaskyYAQmUP2ERETgAIHiO2op aWv4j1EAT1bLMsizXhDDZpXBl9QjaMe1uqewTTXUf9OFfjpWGsG/Zt1DSGpDLZBRvqGE FDzly7NeuSqiEzm1LIHbeA6QEDm5Wj7v5iUyv12rZVx2RHdZminNVeuFbygOaEBmHhc3 bnOg== X-Gm-Message-State: AOAM53320YF1k6A4W8StlVxo7J4jk46yz3Pk9aK3g3jq4fIphH0gI3tY zd1B4ZOB10WAz0jEOoOE6q18erLknv048J/hKbJofA== X-Google-Smtp-Source: ABdhPJwwJo/PqxBRwd5KCFkvXvVJ1pkwc3Q0oJ+/uFfZd2nfwctIOfLr3gicUKuKOxujZoyGyHfks+GdmGr4U6SudVQ= X-Received: by 2002:a19:54c:: with SMTP id 73mr1261131lff.551.1610558024794; Wed, 13 Jan 2021 09:13:44 -0800 (PST) MIME-Version: 1.0 References: <20210112165750.30475-1-peter.maydell@linaro.org> <20210112165750.30475-19-peter.maydell@linaro.org> In-Reply-To: From: Hao Wu Date: Wed, 13 Jan 2021 09:13:33 -0800 Message-ID: Subject: Re: [PULL 18/21] hw/misc: Add a PWM module for NPCM7XX To: Peter Maydell Content-Type: multipart/alternative; boundary="000000000000f5a58305b8cb428e" Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=wuhaotsh@google.com; helo=mail-lf1-x131.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000f5a58305b8cb428e Content-Type: text/plain; charset="UTF-8" On Wed, Jan 13, 2021 at 8:03 AM Peter Maydell wrote: > On Tue, 12 Jan 2021 at 16:58, Peter Maydell > wrote: > > > > From: Hao Wu > > > > The PWM module is part of NPCM7XX module. Each NPCM7XX module has two > > identical PWM modules. Each module contains 4 PWM entries. Each PWM has > > two outputs: frequency and duty_cycle. Both are computed using inputs > > from software side. > > Hi; Coverity reports a possibly-overflowing arithmetic operation here > (CID 1442342): > > > +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p) > > +{ > > + uint64_t duty; > > + > > + if (p->running) { > > + if (p->cnr == 0) { > > + duty = 0; > > + } else if (p->cmr >= p->cnr) { > > + duty = NPCM7XX_PWM_MAX_DUTY; > > + } else { > > + duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1); > > Here all of p->cmr, p->cnr and NPCM7XX_PWM_MAX_DUTY are 32-bits, > so we calculate the whole expression using 32-bit arithmetic > before assigning it to a 64-bit variable. This could be > fixed using eg a cast of NPCM7XX_PWM_MAX_DUTY to uint64_t. > > Incidentally, we don't actually do any 64-bit > arithmetic calculations on 'duty' and we return > a uint32_t from this function, so 'duty' itself could > be a uint32_t, I think... > Since NPCM7XX_PWM_MAX_DUTY =1,000,000 and p->cmr can have up to 65535, The overflow is possible. We might want to cast NPCM7XX_PWM_MAX_DUTY to uint64_t or #define NPCM7XX_PWM_MAX_DUTY 1000000ULL duty itself could be a uint32_t as you point out. Since p->cmr is less than p->cnr in this line, duty cannot exceed NPCM7XX_PWM_MAX_DUTY, so there's no overflow after this computation. Thank you for finding this! Hao > > > + } > > + } else { > > + duty = 0; > > + } > > + > > + if (p->inverted) { > > + duty = NPCM7XX_PWM_MAX_DUTY - duty; > > + } > > + > > + return duty; > > +} > > thanks > -- PMM > --000000000000f5a58305b8cb428e Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Wed, Jan 13, 2021 at 8:03 AM Peter= Maydell <peter.maydell@lina= ro.org> wrote:
On Tue, 12 Jan 2021 at 16:58, Peter Maydell <peter.maydell@linaro.org> w= rote:
>
> From: Hao Wu <wuhaotsh@google.com>
>
> The PWM module is part of NPCM7XX module. Each NPCM7XX module has two<= br> > identical PWM modules. Each module contains 4 PWM entries. Each PWM ha= s
> two outputs: frequency and duty_cycle. Both are computed using inputs<= br> > from software side.

Hi; Coverity reports a possibly-overflowing arithmetic operation here
(CID 1442342):

> +static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
> +{
> +=C2=A0 =C2=A0 uint64_t duty;
> +
> +=C2=A0 =C2=A0 if (p->running) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (p->cnr =3D=3D 0) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 duty =3D 0;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (p->cmr >=3D p->cnr) {=
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 duty =3D NPCM7XX_PWM_MAX_DU= TY;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 duty =3D NPCM7XX_PWM_MAX_DU= TY * (p->cmr + 1) / (p->cnr + 1);

Here all of p->cmr, p->cnr and NPCM7XX_PWM_MAX_DUTY are 32-bits,
so we calculate the whole expression using 32-bit arithmetic
before assigning it to a 64-bit variable. This could be
fixed using eg a cast of NPCM7XX_PWM_MAX_DUTY to uint64_t.

Incidentally, we don't actually do any 64-bit
arithmetic calculations on 'duty' and we return
a uint32_t from this function, so 'duty' itself could
be a uint32_t, I think...
Since NPCM7XX_PWM_MAX_DUTY = =3D1,000,000 and p->cmr can have up to 65535, The overflow is possible. = We might want to cast NPCM7XX_PWM_MAX_DUTY to uint64_t or #define NPCM7XX_P= WM_MAX_DUTY 1000000ULL
duty itself could be a uint32_t as you poi= nt out. Since p->cmr is less than p->cnr in this line, duty cannot ex= ceed NPCM7XX_PWM_MAX_DUTY, so there's no overflow after this computatio= n.

Thank you for finding this!

Hao

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 duty =3D 0;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 if (p->inverted) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 duty =3D NPCM7XX_PWM_MAX_DUTY - duty;
> +=C2=A0 =C2=A0 }
> +
> +=C2=A0 =C2=A0 return duty;
> +}

thanks
-- PMM
--000000000000f5a58305b8cb428e--