From: alvise rigo <a.rigo@virtualopensystems.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: mttcg@greensocs.com,
"Claudio Fontana" <claudio.fontana@huawei.com>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Jani Kokkonen" <jani.kokkonen@huawei.com>,
"VirtualOpenSystems Technical Team" <tech@virtualopensystems.com>,
"Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [RFC v4 1/9] exec.c: Add new exclusive bitmap to ram_list
Date: Tue, 11 Aug 2015 18:11:12 +0200 [thread overview]
Message-ID: <CAH47eN2xF-=kJ27eTQuuwgvdSP2=dC12eUS1VxK70VpKopeNeg@mail.gmail.com> (raw)
In-Reply-To: <55CA1AF8.1090409@redhat.com>
On Tue, Aug 11, 2015 at 5:55 PM, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
>
> On 11/08/2015 17:54, alvise rigo wrote:
>> This can lead to an excessive rate of flush requests, since for one
>> CPU that removes the TLB_EXCL flag, all the others that are competing
>> for the same excl address will need to flush the entire cache and
>> start all over again.
>
> Why flush the entire cache (I understand you mean TLB)?
Sorry, I meant the TLB.
If for each removal of an exclusive entry we set also the bit to 1, we
force the following LL to make a tlb_flush() on every vCPU.
alvise
>
> Paolo
>
>> If for a start we want to have a simpler implementation, I can revert
>> back to the one-bit design.
next prev parent reply other threads:[~2015-08-11 16:11 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-07 17:03 [Qemu-devel] [RFC v4 0/9] Slow-path for atomic instruction translation Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 1/9] exec.c: Add new exclusive bitmap to ram_list Alvise Rigo
2015-08-11 13:52 ` Paolo Bonzini
2015-08-11 14:24 ` Peter Maydell
2015-08-11 14:34 ` alvise rigo
2015-08-11 15:54 ` alvise rigo
2015-08-11 15:55 ` Paolo Bonzini
2015-08-11 16:11 ` alvise rigo [this message]
2015-08-11 16:32 ` Paolo Bonzini
2015-08-12 7:31 ` alvise rigo
2015-08-12 12:36 ` Paolo Bonzini
2015-08-12 13:02 ` Peter Maydell
2015-08-12 14:04 ` alvise rigo
2015-08-12 14:10 ` Paolo Bonzini
2015-08-12 14:32 ` alvise rigo
2015-09-10 13:04 ` alvise rigo
2015-09-10 16:19 ` Alex Bennée
2015-09-10 17:36 ` alvise rigo
2015-09-10 16:25 ` Paolo Bonzini
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 2/9] softmmu: Add new TLB_EXCL flag Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 3/9] softmmu: Add helpers for a new slowpath Alvise Rigo
2015-08-11 13:32 ` alvise rigo
2015-08-11 13:52 ` Paolo Bonzini
2015-08-11 15:55 ` alvise rigo
2015-08-12 12:43 ` Paolo Bonzini
2015-08-12 13:09 ` alvise rigo
2015-08-12 13:14 ` Paolo Bonzini
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 4/9] tcg-op: create new TCG qemu_{ld, st} excl variants Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 5/9] configure: Enable/disable new qemu_{ld, st} excl insns Alvise Rigo
2015-08-08 12:44 ` Aurelien Jarno
2015-08-08 13:57 ` Peter Maydell
2015-08-09 8:11 ` Alex Bennée
2015-08-09 8:40 ` Aurelien Jarno
2015-08-09 9:51 ` Alex Bennée
2015-08-09 10:13 ` Aurelien Jarno
2015-08-09 16:27 ` Alex Bennée
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 6/9] tcg-i386: Implement excl variants of qemu_{ld, st} Alvise Rigo
2015-08-08 13:00 ` Aurelien Jarno
2015-08-10 7:50 ` alvise rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 7/9] tcg-arm: " Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 8/9] tcg-aarch64: " Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 9/9] target-arm: translate: Use ld/st excl for atomic insns Alvise Rigo
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