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* [v2 0/5] Add ISA extension smcntrpmf support
@ 2023-12-29  0:49 Atish Patra
  2023-12-29  0:49 ` [v2 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Atish Patra
                   ` (4 more replies)
  0 siblings, 5 replies; 16+ messages in thread
From: Atish Patra @ 2023-12-29  0:49 UTC (permalink / raw)
  To: qemu-devel
  Cc: Alistair Francis, Bin Meng, Daniel Henrique Barboza, Liu Zhiwei,
	Palmer Dabbelt, qemu-riscv, Weiwei Li, kaiwenxue1

This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. It is based on Kevin's earlier work but improves
it by actually implement privilege mode filtering by tracking the privilege
mode switches. This enables the privilege mode filtering for mhpmcounters as
well. However, Smcntrpmf/Sscofpmf must be enabled to leverage this. This series
also modified to report the raw instruction count instead of virtual cpu time
based on the instruction count when icount is enabled. The former seems to be
the preferred approach for instruction count for other architectures as well.

Please let me know if anybody thinks that's incorrect.

The series is also available at


Changes from v1->v2:
1. Implemented actual mode filtering for both icount and host ticks mode.
1. Addressed comments in v1.
2. Added Kevin's personal email address.

[1] https://github.com/riscv/riscv-smcntrpmf
[2] https://github.com/atishp04/qemu/tree/smcntrpmf_v1

Atish Patra (2):
target/riscv: Fix the predicate functions for mhpmeventhX CSRs
target/riscv: Implement privilege mode filtering for cycle/instret

Kaiwen Xue (3):
target/riscv: Add cycle & instret privilege mode filtering properties
target/riscv: Add cycle & instret privilege mode filtering definitions
target/riscv: Add cycle & instret privilege mode filtering support

target/riscv/cpu.c        |   3 +-
target/riscv/cpu.h        |  17 +++
target/riscv/cpu_bits.h   |  29 +++++
target/riscv/cpu_cfg.h    |   1 +
target/riscv/cpu_helper.c |   9 +-
target/riscv/csr.c        | 245 ++++++++++++++++++++++++++++++--------
target/riscv/pmu.c        |  43 +++++++
target/riscv/pmu.h        |   2 +
8 files changed, 295 insertions(+), 54 deletions(-)

--
2.34.1



^ permalink raw reply	[flat|nested] 16+ messages in thread
* [v2 0/5] Add ISA extension smcntrpmf support
@ 2023-12-29  0:47 Atish Patra
  2023-12-29  0:47 ` [v2 2/5] target/riscv: Add cycle & instret privilege mode filtering properties Atish Patra
  0 siblings, 1 reply; 16+ messages in thread
From: Atish Patra @ 2023-12-29  0:47 UTC (permalink / raw)
  To: qemu-devel

This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. It is based on Kevin's earlier work but improves
it by actually implement privilege mode filtering by tracking the privilege
mode switches. This enables the privilege mode filtering for mhpmcounters as
well. However, Smcntrpmf/Sscofpmf must be enabled to leverage this. This series
also modified to report the raw instruction count instead of virtual cpu time
based on the instruction count when icount is enabled. The former seems to be
the preferred approach for instruction count for other architectures as well.

Please let me know if anybody thinks that's incorrect.

The series is also available at


Changes from v1->v2:
1. Implemented actual mode filtering for both icount and host ticks mode.
1. Addressed comments in v1.
2. Added Kevin's personal email address.

[1] https://github.com/riscv/riscv-smcntrpmf
[2] https://github.com/atishp04/qemu/tree/smcntrpmf_v1

Atish Patra (2):
target/riscv: Fix the predicate functions for mhpmeventhX CSRs
target/riscv: Implement privilege mode filtering for cycle/instret

Kaiwen Xue (3):
target/riscv: Add cycle & instret privilege mode filtering properties
target/riscv: Add cycle & instret privilege mode filtering definitions
target/riscv: Add cycle & instret privilege mode filtering support

target/riscv/cpu.c        |   3 +-
target/riscv/cpu.h        |  17 +++
target/riscv/cpu_bits.h   |  29 +++++
target/riscv/cpu_cfg.h    |   1 +
target/riscv/cpu_helper.c |   9 +-
target/riscv/csr.c        | 245 ++++++++++++++++++++++++++++++--------
target/riscv/pmu.c        |  43 +++++++
target/riscv/pmu.h        |   2 +
8 files changed, 295 insertions(+), 54 deletions(-)

--
2.34.1



^ permalink raw reply	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2024-01-05 22:14 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-12-29  0:49 [v2 0/5] Add ISA extension smcntrpmf support Atish Patra
2023-12-29  0:49 ` [v2 1/5] target/riscv: Fix the predicate functions for mhpmeventhX CSRs Atish Patra
2024-01-03 20:11   ` Daniel Henrique Barboza
2024-01-05  2:43   ` Alistair Francis
2023-12-29  0:49 ` [v2 2/5] target/riscv: Add cycle & instret privilege mode filtering properties Atish Patra
2024-01-03 20:11   ` Daniel Henrique Barboza
2024-01-03 23:26     ` Atish Kumar Patra
2023-12-29  0:49 ` [v2 3/5] target/riscv: Add cycle & instret privilege mode filtering definitions Atish Patra
2024-01-05  2:45   ` Alistair Francis
2024-01-05 22:14     ` Atish Kumar Patra
2023-12-29  0:49 ` [v2 4/5] target/riscv: Add cycle & instret privilege mode filtering support Atish Patra
2024-01-03 20:18   ` Daniel Henrique Barboza
2024-01-03 23:27     ` Atish Kumar Patra
2023-12-29  0:49 ` [v2 5/5] target/riscv: Implement privilege mode filtering for cycle/instret Atish Patra
2024-01-03 20:22   ` Daniel Henrique Barboza
  -- strict thread matches above, loose matches on Subject: below --
2023-12-29  0:47 [v2 0/5] Add ISA extension smcntrpmf support Atish Patra
2023-12-29  0:47 ` [v2 2/5] target/riscv: Add cycle & instret privilege mode filtering properties Atish Patra

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