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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=atishp@rivosinc.com; helo=mail-lj1-x229.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Aug 5, 2024 at 5:12=E2=80=AFPM Alistair Francis wrote: > > On Wed, Jul 24, 2024 at 9:31=E2=80=AFAM Atish Patra = wrote: > > > > As per the ratified AIA spec v1.0, three stateen bits control AIA CSR > > access. > > > > Bit 60 controls the indirect CSRs > > Bit 59 controls the most AIA CSR state > > Bit 58 controls the IMSIC state such as stopei and vstopei > > > > Enable the corresponding bits in [m|h]stateen and enable corresponding > > checks in the CSR accessor functions. > > > > Signed-off-by: Atish Patra > > --- > > target/riscv/csr.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++= +++++++- > > 1 file changed, 87 insertions(+), 1 deletion(-) > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 58be8bc3cc8c..18b9ae802b15 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -316,19 +316,42 @@ static RISCVException smode32(CPURISCVState *env,= int csrno) > > > > static RISCVException aia_smode(CPURISCVState *env, int csrno) > > { > > + int ret; > > + > > if (!riscv_cpu_cfg(env)->ext_ssaia) { > > return RISCV_EXCP_ILLEGAL_INST; > > } > > > > + if (csrno =3D=3D CSR_STOPEI) { > > + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC); > > + } else { > > + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); > > + } > > + > > + if (ret !=3D RISCV_EXCP_NONE) { > > + return ret; > > + } > > + > > return smode(env, csrno); > > } > > > > static RISCVException aia_smode32(CPURISCVState *env, int csrno) > > { > > + int ret; > > + > > if (!riscv_cpu_cfg(env)->ext_ssaia) { > > return RISCV_EXCP_ILLEGAL_INST; > > } > > > > + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); > > + if (ret !=3D RISCV_EXCP_NONE) { > > + return ret; > > + } > > + > > + if (ret !=3D RISCV_EXCP_NONE) { > > + return ret; > > + } > > + > > return smode32(env, csrno); > > } > > > > @@ -567,15 +590,38 @@ static RISCVException pointer_masking(CPURISCVSta= te *env, int csrno) > > > > static RISCVException aia_hmode(CPURISCVState *env, int csrno) > > { > > + int ret; > > + > > if (!riscv_cpu_cfg(env)->ext_ssaia) { > > return RISCV_EXCP_ILLEGAL_INST; > > } > > > > - return hmode(env, csrno); > > + if (csrno =3D=3D CSR_VSTOPEI) { > > + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC); > > + } else { > > + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); > > + } > > + > > + if (ret !=3D RISCV_EXCP_NONE) { > > + return ret; > > + } > > + > > + return hmode(env, csrno); > > } > > > > static RISCVException aia_hmode32(CPURISCVState *env, int csrno) > > { > > + int ret; > > + > > + if (!riscv_cpu_cfg(env)->ext_ssaia) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); > > + if (ret !=3D RISCV_EXCP_NONE) { > > + return ret; > > + } > > + > > if (!riscv_cpu_cfg(env)->ext_ssaia) { > > return RISCV_EXCP_ILLEGAL_INST; > > } > > @@ -1992,6 +2038,12 @@ static RISCVException rmw_xiselect(CPURISCVState= *env, int csrno, > > target_ulong wr_mask) > > { > > target_ulong *iselect; > > + int ret; > > + > > + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); > > + if (ret !=3D RISCV_EXCP_NONE) { > > + return ret; > > + } > > > > /* Translate CSR number for VS-mode */ > > csrno =3D csrind_xlate_vs_csrno(env, csrno); > > @@ -2162,6 +2214,11 @@ static RISCVException rmw_xireg(CPURISCVState *e= nv, int csrno, > > int ret =3D -EINVAL; > > target_ulong isel; > > > > + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); > > + if (ret !=3D RISCV_EXCP_NONE) { > > + return ret; > > + } > > + > > /* Translate CSR number for VS-mode */ > > csrno =3D csrind_xlate_vs_csrno(env, csrno); > > > > @@ -2610,6 +2667,22 @@ static RISCVException write_mstateen0(CPURISCVSt= ate *env, int csrno, > > if (env->priv_ver >=3D PRIV_VERSION_1_13_0) { > > wr_mask |=3D SMSTATEEN0_P1P13; > > } > > + /* > > + * TODO: Do we need to check ssaia as well ? Can we enable ssaia w= ithout > > + * smaia ? > > + */ > > + if (riscv_cpu_cfg(env)->ext_smaia) { > > + wr_mask |=3D SMSTATEEN0_SVSLCT; > > + } > > This looks right to me, do we need the TODO? > cool. I will remove the TODO. > Otherwise > > Reviewed-by: Alistair Francis > > Alistair