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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Aurelien Jarno , "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000cd70dc05acc67449 Content-Type: text/plain; charset="UTF-8" On Thursday, August 13, 2020, Kaige Li wrote: > This will help ensure that style guidelines are being maintained during > subsequent changes. > > Signed-off-by: Kaige Li > --- Agreed. Reviewed-by: Aleksandar Markovic > target/mips/translate_init.inc.c | 61 ++++++++++++++++++++---------- > ---------- > 1 file changed, 31 insertions(+), 30 deletions(-) > > diff --git a/target/mips/translate_init.inc.c > b/target/mips/translate_init.inc.c > index 637cacc..0740819 100644 > --- a/target/mips/translate_init.inc.c > +++ b/target/mips/translate_init.inc.c > @@ -53,8 +53,7 @@ > > /*********************************************************** > ******************/ > /* MIPS CPU definitions */ > -const mips_def_t mips_defs[] = > -{ > +const mips_def_t mips_defs[] = { > { > .name = "4Kc", > .CP0_PRid = 0x00018000, > @@ -766,8 +765,8 @@ const mips_def_t mips_defs[] = > .name = "Loongson-2E", > .CP0_PRid = 0x6302, > /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. > */ > - .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | > - (0x1<<5) | (0x1<<4) | (0x1<<1), > + .CP0_Config0 = (0x1 << 17) | (0x1 << 16) | (0x1 << 11) | (0x1 << > 8) | > + (0x1 << 5) | (0x1 << 4) | (0x1 << 1), > /* Note: Config1 is only used internally, > Loongson-2E has only Config0. */ > .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), > @@ -786,8 +785,8 @@ const mips_def_t mips_defs[] = > .name = "Loongson-2F", > .CP0_PRid = 0x6303, > /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. > */ > - .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | > - (0x1<<5) | (0x1<<4) | (0x1<<1), > + .CP0_Config0 = (0x1 << 17) | (0x1 << 16) | (0x1 << 11) | (0x1 << > 8) | > + (0x1 << 5) | (0x1 << 4) | (0x1 << 1), > /* Note: Config1 is only used internally, > Loongson-2F has only Config0. */ > .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), > @@ -932,19 +931,19 @@ void mips_cpu_list(void) > } > > #ifndef CONFIG_USER_ONLY > -static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) > +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) > { > env->tlb->nb_tlb = 1; > env->tlb->map_address = &no_mmu_map_address; > } > > -static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) > +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) > { > env->tlb->nb_tlb = 1; > env->tlb->map_address = &fixed_mmu_map_address; > } > > -static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) > +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) > { > env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); > env->tlb->map_address = &r4k_map_address; > @@ -956,40 +955,41 @@ static void r4k_mmu_init (CPUMIPSState *env, const > mips_def_t *def) > env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; > } > > -static void mmu_init (CPUMIPSState *env, const mips_def_t *def) > +static void mmu_init(CPUMIPSState *env, const mips_def_t *def) > { > env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); > > switch (def->mmu_type) { > - case MMU_TYPE_NONE: > - no_mmu_init(env, def); > - break; > - case MMU_TYPE_R4000: > - r4k_mmu_init(env, def); > - break; > - case MMU_TYPE_FMT: > - fixed_mmu_init(env, def); > - break; > - case MMU_TYPE_R3000: > - case MMU_TYPE_R6000: > - case MMU_TYPE_R8000: > - default: > - cpu_abort(env_cpu(env), "MMU type not supported\n"); > + case MMU_TYPE_NONE: > + no_mmu_init(env, def); > + break; > + case MMU_TYPE_R4000: > + r4k_mmu_init(env, def); > + break; > + case MMU_TYPE_FMT: > + fixed_mmu_init(env, def); > + break; > + case MMU_TYPE_R3000: > + case MMU_TYPE_R6000: > + case MMU_TYPE_R8000: > + default: > + cpu_abort(env_cpu(env), "MMU type not supported\n"); > } > } > #endif /* CONFIG_USER_ONLY */ > > -static void fpu_init (CPUMIPSState *env, const mips_def_t *def) > +static void fpu_init(CPUMIPSState *env, const mips_def_t *def) > { > int i; > > - for (i = 0; i < MIPS_FPU_MAX; i++) > + for (i = 0; i < MIPS_FPU_MAX; i++) { > env->fpus[i].fcr0 = def->CP1_fcr0; > + } > > memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); > } > > -static void mvp_init (CPUMIPSState *env, const mips_def_t *def) > +static void mvp_init(CPUMIPSState *env, const mips_def_t *def) > { > env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); > > @@ -999,9 +999,10 @@ static void mvp_init (CPUMIPSState *env, const > mips_def_t *def) > implemented, 5 TCs implemented. */ > env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | > (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | > -// TODO: actually do 2 VPEs. > -// (1 << CP0MVPC0_TCA) | (0x1 << > CP0MVPC0_PVPE) | > -// (0x04 << CP0MVPC0_PTC); > +/* TODO: actually do 2 VPEs. > + * (1 << CP0MVPC0_TCA) | (0x1 << > CP0MVPC0_PVPE) | > + * (0x04 << CP0MVPC0_PTC); > + */ > (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) > | > (0x00 << CP0MVPC0_PTC); > #if !defined(CONFIG_USER_ONLY) > -- > 2.1.0 > > --000000000000cd70dc05acc67449 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

On Thursday, August 13, 2020, Kaige Li <likaige@loongson.cn> wrote:
This will help ensure that style guidelines are being maintained d= uring
subsequent changes.

Signed-off-by: Kaige Li <likaige@= loongson.cn>
---

Agreed.

Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
= =C2=A0
=C2=A0target/mips/translate_init.inc.c | 61 ++++++++++++++++++++------= --------------
=C2=A01 file changed, 31 insertions(+), 30 deletions(-)

diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_= init.inc.c
index 637cacc..0740819 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -53,8 +53,7 @@

=C2=A0/*****************************************************************************/
=C2=A0/* MIPS CPU definitions */
-const mips_def_t mips_defs[] =3D
-{
+const mips_def_t mips_defs[] =3D {
=C2=A0 =C2=A0 =C2=A0{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.name =3D "4Kc",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.CP0_PRid =3D 0x00018000,
@@ -766,8 +765,8 @@ const mips_def_t mips_defs[] =3D
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.name =3D "Loongson-2E",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.CP0_PRid =3D 0x6302,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* 64KB I-cache and d-cache. 4 way with 3= 2 bit cache line size.=C2=A0 */
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 .CP0_Config0 =3D (0x1<<17) | (0x1<<= ;16) | (0x1<<11) | (0x1<<8) |
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0(0x1<<5) | (0x1<<4) | (0x1<<1),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .CP0_Config0 =3D (0x1 << 17) | (0x1 <= < 16) | (0x1 << 11) | (0x1 << 8) |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0(0x1 << 5) | (0x1 << 4) | (0x1 << 1),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Note: Config1 is only used internally,=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Loongson-2E has only Config0.=C2= =A0 */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.CP0_Config1 =3D (1 << CP0C1_FP) | = (47 << CP0C1_MMU),
@@ -786,8 +785,8 @@ const mips_def_t mips_defs[] =3D
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.name =3D "Loongson-2F",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.CP0_PRid =3D 0x6303,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* 64KB I-cache and d-cache. 4 way with 3= 2 bit cache line size.=C2=A0 */
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 .CP0_Config0 =3D (0x1<<17) | (0x1<<= ;16) | (0x1<<11) | (0x1<<8) |
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0(0x1<<5) | (0x1<<4) | (0x1<<1),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .CP0_Config0 =3D (0x1 << 17) | (0x1 <= < 16) | (0x1 << 11) | (0x1 << 8) |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0(0x1 << 5) | (0x1 << 4) | (0x1 << 1),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Note: Config1 is only used internally,=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Loongson-2F has only Config0.=C2= =A0 */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.CP0_Config1 =3D (1 << CP0C1_FP) | = (47 << CP0C1_MMU),
@@ -932,19 +931,19 @@ void mips_cpu_list(void)
=C2=A0}

=C2=A0#ifndef CONFIG_USER_ONLY
-static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0env->tlb->nb_tlb =3D 1;
=C2=A0 =C2=A0 =C2=A0env->tlb->map_address =3D &no_mmu_map_address= ;
=C2=A0}

-static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0env->tlb->nb_tlb =3D 1;
=C2=A0 =C2=A0 =C2=A0env->tlb->map_address =3D &fixed_mmu_map_addr= ess;
=C2=A0}

-static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0env->tlb->nb_tlb =3D 1 + ((def->CP0_Config1 &g= t;> CP0C1_MMU) & 63);
=C2=A0 =C2=A0 =C2=A0env->tlb->map_address =3D &r4k_map_address; @@ -956,40 +955,41 @@ static void r4k_mmu_init (CPUMIPSState *env, const mi= ps_def_t *def)
=C2=A0 =C2=A0 =C2=A0env->tlb->helper_tlbinvf =3D r4k_helper_tlbinvf;<= br> =C2=A0}

-static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
+static void mmu_init(CPUMIPSState *env, const mips_def_t *def)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0env->tlb =3D g_malloc0(sizeof(CPUMIPSTLBContext= ));

=C2=A0 =C2=A0 =C2=A0switch (def->mmu_type) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MMU_TYPE_NONE:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 no_mmu_init(env, def);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MMU_TYPE_R4000:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 r4k_mmu_init(env, def);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MMU_TYPE_FMT:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 fixed_mmu_init(env, def);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MMU_TYPE_R3000:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MMU_TYPE_R6000:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 case MMU_TYPE_R8000:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 default:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_abort(env_cpu(env), "MM= U type not supported\n");
+=C2=A0 =C2=A0 case MMU_TYPE_NONE:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 no_mmu_init(env, def);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case MMU_TYPE_R4000:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 r4k_mmu_init(env, def);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case MMU_TYPE_FMT:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 fixed_mmu_init(env, def);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case MMU_TYPE_R3000:
+=C2=A0 =C2=A0 case MMU_TYPE_R6000:
+=C2=A0 =C2=A0 case MMU_TYPE_R8000:
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_abort(env_cpu(env), "MMU type not sup= ported\n");
=C2=A0 =C2=A0 =C2=A0}
=C2=A0}
=C2=A0#endif /* CONFIG_USER_ONLY */

-static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
+static void fpu_init(CPUMIPSState *env, const mips_def_t *def)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0int i;

-=C2=A0 =C2=A0 for (i =3D 0; i < MIPS_FPU_MAX; i++)
+=C2=A0 =C2=A0 for (i =3D 0; i < MIPS_FPU_MAX; i++) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->fpus[i].fcr0 =3D def->CP1_fcr0= ;
+=C2=A0 =C2=A0 }

=C2=A0 =C2=A0 =C2=A0memcpy(&env->active_fpu, &env->fpus[0], s= izeof(env->active_fpu));
=C2=A0}

-static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
+static void mvp_init(CPUMIPSState *env, const mips_def_t *def)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0env->mvp =3D g_malloc0(sizeof(CPUMIPSMVPContext= ));

@@ -999,9 +999,10 @@ static void mvp_init (CPUMIPSState *env, const mips_de= f_t *def)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 implemented, 5 TCs implemented. */
=C2=A0 =C2=A0 =C2=A0env->mvp->CP0_MVPConf0 =3D (1U << CP0MVPC0_= M) | (1 << CP0MVPC0_TLBS) |
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0 << CP0MVPC0_GS) | (1 << CP0M= VPC0_PCP) |
-// TODO: actually do 2 VPEs.
-//=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << CP0MVPC0_TCA) | (0x1 <<= CP0MVPC0_PVPE) |
-//=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0x04 << CP0MVPC0_PTC);
+/* TODO: actually do 2 VPEs.
+ *=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << CP0MVPC0_TCA) | (0x1 << CP0MV= PC0_PVPE) |
+ *=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x04 << CP0MVPC0_PTC);
+ */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << CP0MVPC0_TCA) | (0x0 << C= P0MVPC0_PVPE) |
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (0x00 << CP0MVPC0_PTC);
=C2=A0#if !defined(CONFIG_USER_ONLY)
--
2.1.0

--000000000000cd70dc05acc67449--