[PATCH 0/4] Basic TCG Loongson-3A1000 Support

[PATCH 0/4] Basic TCG Loongson-3A1000 Support

[Jiaxun Yang]

This series is the sucessor of
"target/mips: Add loongson gs464 core" [1].

Based on Huacai's CPU define.
Boot test have been performed with Huacai's KVM series.

Note: This series only adds instructions that can be generated by GCC,
as we're relying on toolchain for documents of these instructions.  

[1]: https://patchwork.kernel.org/cover/11457385/

Thanks.

Jiaxun Yang (4):
  target/mips: Legalize Loongson insn flags
  target/mips: Add comments for vendor-specific ASEs
  target/mips: Add loongson ext lsdc2 instrustions
  target/mips: Add loongson ext lswc2 instrustions

 target/mips/mips-defs.h |   8 +-
 target/mips/translate.c | 442 +++++++++++++++++++++++++++++++++++++++-
 2 files changed, 442 insertions(+), 8 deletions(-)

-- 
2.27.0

[PATCH 1/4] target/mips: Legalize Loongson insn flags

[Jiaxun Yang]

To match the actual status of Loongson insn, we split flags
for LMMI and LEXT from INSN_LOONGSON2F.

As Loongson-2F only implemented interger part of LEXT, we'll
not enable LEXT for the processor, but instead we're still using
INSN_LOONGSON2F as switch flag of these instructions.

All multimedia instructions have been moved to LMMI flag. Loongson-2F
and Loongson-3A are sharing these instructions.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/mips/mips-defs.h |  4 ++--
 target/mips/translate.c | 13 +++++++------
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 0c129106c8..f1b833f947 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -70,7 +70,7 @@
 #define CPU_VR54XX      (CPU_MIPS4 | INSN_VR54XX)
 #define CPU_R5900       (CPU_MIPS3 | INSN_R5900)
 #define CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)
-#define CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F)
+#define CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
 
 #define CPU_MIPS5       (CPU_MIPS4 | ISA_MIPS5)
 
@@ -97,7 +97,7 @@
 /* Wave Computing: "nanoMIPS" */
 #define CPU_NANOMIPS32  (CPU_MIPS32R6 | ISA_NANOMIPS32)
 
-#define CPU_LOONGSON3A  (CPU_MIPS64R2 | INSN_LOONGSON3A)
+#define CPU_LOONGSON3A  (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
 
 /*
  * Strictly follow the architecture standard:
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2caf4cba5a..e49f32f6ae 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1046,7 +1046,7 @@ enum {
     OPC_BC2NEZ  = (0x0D << 21) | OPC_CP2,
 };
 
-#define MASK_LMI(op)    (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
+#define MASK_LMMI(op)    (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
 
 enum {
     OPC_PADDSH      = (24 << 21) | (0x00) | OPC_CP2,
@@ -3421,7 +3421,8 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
     TCGv t0, t1, t2;
     int mem_idx = ctx->mem_idx;
 
-    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
+    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
+                                      INSN_LOONGSON3A)) {
         /*
          * Loongson CPU uses a load to zero register for prefetch.
          * We emulate it as a NOP. On other CPU we must perform the
@@ -5531,7 +5532,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
     TCGv_i64 t0, t1;
     TCGCond cond;
 
-    opc = MASK_LMI(ctx->opcode);
+    opc = MASK_LMMI(ctx->opcode);
     switch (opc) {
     case OPC_ADD_CP2:
     case OPC_SUB_CP2:
@@ -27161,7 +27162,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MULTU_G_2F:
     case OPC_MOD_G_2F:
     case OPC_MODU_G_2F:
-        check_insn(ctx, INSN_LOONGSON2F);
+        check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
         gen_loongson_integer(ctx, op1, rd, rs, rt);
         break;
     case OPC_CLO:
@@ -27194,7 +27195,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
     case OPC_DDIVU_G_2F:
     case OPC_DMOD_G_2F:
     case OPC_DMODU_G_2F:
-        check_insn(ctx, INSN_LOONGSON2F);
+        check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
         gen_loongson_integer(ctx, op1, rd, rs, rt);
         break;
 #endif
@@ -30641,7 +30642,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case OPC_CP2:
-        check_insn(ctx, INSN_LOONGSON2F);
+        check_insn(ctx, ASE_LMMI);
         /* Note that these instructions use different fields.  */
         gen_loongson_multimedia(ctx, sa, rd, rt);
         break;
-- 
2.27.0

Re: [PATCH 1/4] target/mips: Legalize Loongson insn flags

[Aleksandar Markovic]

нед, 14. јун 2020. у 10:03 Jiaxun Yang <jiaxun.yang@flygoat.com> је написао/ла:
>
> To match the actual status of Loongson insn, we split flags
> for LMMI and LEXT from INSN_LOONGSON2F.
>
> As Loongson-2F only implemented interger part of LEXT, we'll
> not enable LEXT for the processor, but instead we're still using
> INSN_LOONGSON2F as switch flag of these instructions.
>
> All multimedia instructions have been moved to LMMI flag. Loongson-2F
> and Loongson-3A are sharing these instructions.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---

Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>

Applied to the next mips queue.

>  target/mips/mips-defs.h |  4 ++--
>  target/mips/translate.c | 13 +++++++------
>  2 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
> index 0c129106c8..f1b833f947 100644
> --- a/target/mips/mips-defs.h
> +++ b/target/mips/mips-defs.h
> @@ -70,7 +70,7 @@
>  #define CPU_VR54XX      (CPU_MIPS4 | INSN_VR54XX)
>  #define CPU_R5900       (CPU_MIPS3 | INSN_R5900)
>  #define CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)
> -#define CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F)
> +#define CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
>
>  #define CPU_MIPS5       (CPU_MIPS4 | ISA_MIPS5)
>
> @@ -97,7 +97,7 @@
>  /* Wave Computing: "nanoMIPS" */
>  #define CPU_NANOMIPS32  (CPU_MIPS32R6 | ISA_NANOMIPS32)
>
> -#define CPU_LOONGSON3A  (CPU_MIPS64R2 | INSN_LOONGSON3A)
> +#define CPU_LOONGSON3A  (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
>
>  /*
>   * Strictly follow the architecture standard:
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 2caf4cba5a..e49f32f6ae 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1046,7 +1046,7 @@ enum {
>      OPC_BC2NEZ  = (0x0D << 21) | OPC_CP2,
>  };
>
> -#define MASK_LMI(op)    (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
> +#define MASK_LMMI(op)    (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
>
>  enum {
>      OPC_PADDSH      = (24 << 21) | (0x00) | OPC_CP2,
> @@ -3421,7 +3421,8 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
>      TCGv t0, t1, t2;
>      int mem_idx = ctx->mem_idx;
>
> -    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
> +    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
> +                                      INSN_LOONGSON3A)) {
>          /*
>           * Loongson CPU uses a load to zero register for prefetch.
>           * We emulate it as a NOP. On other CPU we must perform the
> @@ -5531,7 +5532,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
>      TCGv_i64 t0, t1;
>      TCGCond cond;
>
> -    opc = MASK_LMI(ctx->opcode);
> +    opc = MASK_LMMI(ctx->opcode);
>      switch (opc) {
>      case OPC_ADD_CP2:
>      case OPC_SUB_CP2:
> @@ -27161,7 +27162,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
>      case OPC_MULTU_G_2F:
>      case OPC_MOD_G_2F:
>      case OPC_MODU_G_2F:
> -        check_insn(ctx, INSN_LOONGSON2F);
> +        check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
>          gen_loongson_integer(ctx, op1, rd, rs, rt);
>          break;
>      case OPC_CLO:
> @@ -27194,7 +27195,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
>      case OPC_DDIVU_G_2F:
>      case OPC_DMOD_G_2F:
>      case OPC_DMODU_G_2F:
> -        check_insn(ctx, INSN_LOONGSON2F);
> +        check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
>          gen_loongson_integer(ctx, op1, rd, rs, rt);
>          break;
>  #endif
> @@ -30641,7 +30642,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
>          }
>          break;
>      case OPC_CP2:
> -        check_insn(ctx, INSN_LOONGSON2F);
> +        check_insn(ctx, ASE_LMMI);
>          /* Note that these instructions use different fields.  */
>          gen_loongson_multimedia(ctx, sa, rd, rt);
>          break;
> --
> 2.27.0

[PATCH 2/4] target/mips: Add comments for vendor-specific ASEs

[Jiaxun Yang]

Abbreviations of vendor-specific ASEs looks very similiar.
Add comments to explain the full name and vendors of these flags.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/mips/mips-defs.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index f1b833f947..ed6a7a9e54 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -57,9 +57,13 @@
 /*
  *   bits 52-63: vendor-specific ASEs
  */
+/* MultiMedia Instructions defined by R5900 */
 #define ASE_MMI           0x0010000000000000ULL
+/* MIPS eXtension/enhanced Unit defined by Ingenic */
 #define ASE_MXU           0x0020000000000000ULL
+/* Loongson MultiMedia Instructions */
 #define ASE_LMMI          0x0040000000000000ULL
+/* Loongson EXTensions */
 #define ASE_LEXT          0x0080000000000000ULL
 
 /* MIPS CPU defines. */
-- 
2.27.0

Re: [PATCH 2/4] target/mips: Add comments for vendor-specific ASEs

[Aleksandar Markovic]

нед, 14. јун 2020. у 10:03 Jiaxun Yang <jiaxun.yang@flygoat.com> је написао/ла:
>
> Abbreviations of vendor-specific ASEs looks very similiar.
> Add comments to explain the full name and vendors of these flags.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---

Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>

Applied to the next mips queue.

>  target/mips/mips-defs.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
> index f1b833f947..ed6a7a9e54 100644
> --- a/target/mips/mips-defs.h
> +++ b/target/mips/mips-defs.h
> @@ -57,9 +57,13 @@
>  /*
>   *   bits 52-63: vendor-specific ASEs
>   */
> +/* MultiMedia Instructions defined by R5900 */
>  #define ASE_MMI           0x0010000000000000ULL
> +/* MIPS eXtension/enhanced Unit defined by Ingenic */
>  #define ASE_MXU           0x0020000000000000ULL
> +/* Loongson MultiMedia Instructions */
>  #define ASE_LMMI          0x0040000000000000ULL
> +/* Loongson EXTensions */
>  #define ASE_LEXT          0x0080000000000000ULL
>
>  /* MIPS CPU defines. */
> --
> 2.27.0

[PATCH 3/4] target/mips: Add loongson ext lsdc2 instrustions

[Jiaxun Yang]

LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
instructions by loongson-ext ASE.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/mips/translate.c | 176 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 176 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index e49f32f6ae..8b45ff37e6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -460,6 +460,24 @@ enum {
     R6_OPC_SCD         = 0x27 | OPC_SPECIAL3,
 };
 
+/* Loongson EXT LDC2/SDC2 opcodes */
+#define MASK_LOONGSON_LSDC2(op)           (MASK_OP_MAJOR(op) | (op & 0x7))
+
+enum {
+    OPC_GSLBX      = 0x0 | OPC_LDC2,
+    OPC_GSLHX      = 0x1 | OPC_LDC2,
+    OPC_GSLWX      = 0x2 | OPC_LDC2,
+    OPC_GSLDX      = 0x3 | OPC_LDC2,
+    OPC_GSLWXC1    = 0x6 | OPC_LDC2,
+    OPC_GSLDXC1    = 0x7 | OPC_LDC2,
+    OPC_GSSBX      = 0x0 | OPC_SDC2,
+    OPC_GSSHX      = 0x1 | OPC_SDC2,
+    OPC_GSSWX      = 0x2 | OPC_SDC2,
+    OPC_GSSDX      = 0x3 | OPC_SDC2,
+    OPC_GSSWXC1    = 0x6 | OPC_SDC2,
+    OPC_GSSDXC1    = 0x7 | OPC_SDC2,
+};
+
 /* BSHFL opcodes */
 #define MASK_BSHFL(op)              (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 
@@ -5910,6 +5928,162 @@ no_rd:
     tcg_temp_free_i64(t1);
 }
 
+/* Loongson EXT LDC2/SDC2 */
+static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
+                                int rs, int rd)
+{
+    int offset = (int8_t)(ctx->opcode >> 3);
+    uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode);
+    TCGv t0, t1;
+    TCGv_i32 fp0;
+
+    /* Pre-conditions */
+    switch (opc) {
+    case OPC_GSLBX:
+    case OPC_GSLHX:
+    case OPC_GSLWX:
+    case OPC_GSLDX:
+        /* prefetch, implement as NOP */
+        if (rt == 0) {
+            return;
+        }
+        break;
+    case OPC_GSSBX:
+    case OPC_GSSHX:
+    case OPC_GSSWX:
+    case OPC_GSSDX:
+        break;
+    case OPC_GSLWXC1:
+    case OPC_GSSWXC1:
+#if defined(TARGET_MIPS64)
+    case OPC_GSLDXC1:
+    case OPC_GSSDXC1:
+#endif
+        check_cp1_enabled(ctx);
+        /* Check prefetch for CP1 load instructions */
+        if ((opc == OPC_GSLDXC1 || opc ==  OPC_GSLWXC1)
+            && rt == 0) {
+            return;
+        }
+        break;
+    default:
+        MIPS_INVAL("loongson_lsdc2");
+        generate_exception_end(ctx, EXCP_RI);
+        return;
+        break;
+    }
+
+    t0 = tcg_temp_new();
+
+    gen_base_offset_addr(ctx, t0, rs, offset);
+    gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+
+    switch (opc) {
+    case OPC_GSLBX:
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
+        gen_store_gpr(t0, rt);
+        break;
+    case OPC_GSLHX:
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, rt);
+        break;
+    case OPC_GSLWX:
+        gen_base_offset_addr(ctx, t0, rs, offset);
+        if (rd) {
+            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+        }
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, rt);
+        break;
+#if defined(TARGET_MIPS64)
+    case OPC_GSLDX:
+        gen_base_offset_addr(ctx, t0, rs, offset);
+        if (rd) {
+            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+        }
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, rt);
+        break;
+#endif
+    case OPC_GSLWXC1:
+        check_cp1_enabled(ctx);
+        gen_base_offset_addr(ctx, t0, rs, offset);
+        if (rd) {
+            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+        }
+        fp0 = tcg_temp_new_i32();
+        tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
+                            ctx->default_tcg_memop_mask);
+        gen_store_fpr32(ctx, fp0, rt);
+        tcg_temp_free_i32(fp0);
+        break;
+#if defined(TARGET_MIPS64)
+    case OPC_GSLDXC1:
+        check_cp1_enabled(ctx);
+        gen_base_offset_addr(ctx, t0, rs, offset);
+        if (rd) {
+            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+        }
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_store_fpr64(ctx, t0, rt);
+        break;
+#endif
+    case OPC_GSSBX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB);
+        tcg_temp_free(t1);
+        break;
+    case OPC_GSSHX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+    case OPC_GSSWX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+#if defined(TARGET_MIPS64)
+    case OPC_GSSDX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+#endif
+    case OPC_GSSWXC1:
+        fp0 = tcg_temp_new_i32();
+        gen_load_fpr32(ctx, fp0, rt);
+        tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free_i32(fp0);
+        break;
+#if defined(TARGET_MIPS64)
+    case OPC_GSSDXC1:
+        t1 = tcg_temp_new();
+        gen_load_fpr64(ctx, t1, rt);
+        tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+#endif
+    default:
+        break;
+    }
+
+    tcg_temp_free(t0);
+}
+
 /* Traps */
 static void gen_trap(DisasContext *ctx, uint32_t opc,
                      int rs, int rt, int16_t imm)
@@ -30635,6 +30809,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
                 /* OPC_JIC, OPC_JIALC */
                 gen_compute_compact_branch(ctx, op, 0, rt, imm);
             }
+        } else if (ctx->insn_flags & ASE_LEXT) {
+            gen_loongson_lsdc2(ctx, rt, rs, rd);
         } else {
             /* OPC_LWC2, OPC_SWC2 */
             /* COP2: Not implemented. */
-- 
2.27.0

Re: [PATCH 3/4] target/mips: Add loongson ext lsdc2 instrustions

[Aleksandar Markovic]

нед, 14. јун 2020. у 10:02 Jiaxun Yang <jiaxun.yang@flygoat.com> је написао/ла:
>
> LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
> instructions by loongson-ext ASE.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---

Please use "group of instructions" instead of just "instructions" in the title.

>  target/mips/translate.c | 176 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 176 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e49f32f6ae..8b45ff37e6 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -460,6 +460,24 @@ enum {
>      R6_OPC_SCD         = 0x27 | OPC_SPECIAL3,
>  };
>
> +/* Loongson EXT LDC2/SDC2 opcodes */
> +#define MASK_LOONGSON_LSDC2(op)           (MASK_OP_MAJOR(op) | (op & 0x7))
> +
> +enum {
> +    OPC_GSLBX      = 0x0 | OPC_LDC2,
> +    OPC_GSLHX      = 0x1 | OPC_LDC2,
> +    OPC_GSLWX      = 0x2 | OPC_LDC2,
> +    OPC_GSLDX      = 0x3 | OPC_LDC2,
> +    OPC_GSLWXC1    = 0x6 | OPC_LDC2,
> +    OPC_GSLDXC1    = 0x7 | OPC_LDC2,
> +    OPC_GSSBX      = 0x0 | OPC_SDC2,
> +    OPC_GSSHX      = 0x1 | OPC_SDC2,
> +    OPC_GSSWX      = 0x2 | OPC_SDC2,
> +    OPC_GSSDX      = 0x3 | OPC_SDC2,
> +    OPC_GSSWXC1    = 0x6 | OPC_SDC2,
> +    OPC_GSSDXC1    = 0x7 | OPC_SDC2,
> +};
> +
>  /* BSHFL opcodes */
>  #define MASK_BSHFL(op)              (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
>
> @@ -5910,6 +5928,162 @@ no_rd:
>      tcg_temp_free_i64(t1);
>  }
>
> +/* Loongson EXT LDC2/SDC2 */
> +static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
> +                                int rs, int rd)
> +{
> +    int offset = (int8_t)(ctx->opcode >> 3);
> +    uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode);
> +    TCGv t0, t1;
> +    TCGv_i32 fp0;
> +
> +    /* Pre-conditions */
> +    switch (opc) {
> +    case OPC_GSLBX:
> +    case OPC_GSLHX:
> +    case OPC_GSLWX:
> +    case OPC_GSLDX:
> +        /* prefetch, implement as NOP */
> +        if (rt == 0) {
> +            return;
> +        }
> +        break;
> +    case OPC_GSSBX:
> +    case OPC_GSSHX:
> +    case OPC_GSSWX:
> +    case OPC_GSSDX:
> +        break;
> +    case OPC_GSLWXC1:
> +    case OPC_GSSWXC1:
> +#if defined(TARGET_MIPS64)
> +    case OPC_GSLDXC1:
> +    case OPC_GSSDXC1:
> +#endif
> +        check_cp1_enabled(ctx);
> +        /* Check prefetch for CP1 load instructions */
> +        if ((opc == OPC_GSLDXC1 || opc ==  OPC_GSLWXC1)
> +            && rt == 0) {
> +            return;
> +        }
> +        break;

I think the segment for the last four instructions got needlessly
complicated and harder to read. Wouldn't this be simpler and clearer,
if written as:

    case OPC_GSLWXC1:
#if defined(TARGET_MIPS64)
    case OPC_GSLDXC1:
#endif
        check_cp1_enabled(ctx);
        if (rt == 0) {
            return;
        }
        break;
    case OPC_GSSWXC1:
#if defined(TARGET_MIPS64)
    case OPC_GSSDXC1:
#endif
        check_cp1_enabled(ctx);
        break;

Please, Jiaxun, convert this segment to the simpler-to-read form I proposed.

The same applies to other similar cases in 3/4 and 4/4 patches, if any.

Thanks,
Aleksandar

> +    default:
> +        MIPS_INVAL("loongson_lsdc2");
> +        generate_exception_end(ctx, EXCP_RI);
> +        return;
> +        break;
> +    }
> +
> +    t0 = tcg_temp_new();
> +
> +    gen_base_offset_addr(ctx, t0, rs, offset);
> +    gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
> +
> +    switch (opc) {
> +    case OPC_GSLBX:
> +        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
> +        gen_store_gpr(t0, rt);
> +        break;
> +    case OPC_GSLHX:
> +        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
> +                            ctx->default_tcg_memop_mask);
> +        gen_store_gpr(t0, rt);
> +        break;
> +    case OPC_GSLWX:
> +        gen_base_offset_addr(ctx, t0, rs, offset);
> +        if (rd) {
> +            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
> +        }
> +        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
> +                            ctx->default_tcg_memop_mask);
> +        gen_store_gpr(t0, rt);
> +        break;
> +#if defined(TARGET_MIPS64)
> +    case OPC_GSLDX:
> +        gen_base_offset_addr(ctx, t0, rs, offset);
> +        if (rd) {
> +            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
> +        }
> +        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
> +                            ctx->default_tcg_memop_mask);
> +        gen_store_gpr(t0, rt);
> +        break;
> +#endif
> +    case OPC_GSLWXC1:
> +        check_cp1_enabled(ctx);
> +        gen_base_offset_addr(ctx, t0, rs, offset);
> +        if (rd) {
> +            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
> +        }
> +        fp0 = tcg_temp_new_i32();
> +        tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
> +                            ctx->default_tcg_memop_mask);
> +        gen_store_fpr32(ctx, fp0, rt);
> +        tcg_temp_free_i32(fp0);
> +        break;
> +#if defined(TARGET_MIPS64)
> +    case OPC_GSLDXC1:
> +        check_cp1_enabled(ctx);
> +        gen_base_offset_addr(ctx, t0, rs, offset);
> +        if (rd) {
> +            gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
> +        }
> +        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
> +                            ctx->default_tcg_memop_mask);
> +        gen_store_fpr64(ctx, t0, rt);
> +        break;
> +#endif
> +    case OPC_GSSBX:
> +        t1 = tcg_temp_new();
> +        gen_load_gpr(t1, rt);
> +        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB);
> +        tcg_temp_free(t1);
> +        break;
> +    case OPC_GSSHX:
> +        t1 = tcg_temp_new();
> +        gen_load_gpr(t1, rt);
> +        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
> +                            ctx->default_tcg_memop_mask);
> +        tcg_temp_free(t1);
> +        break;
> +    case OPC_GSSWX:
> +        t1 = tcg_temp_new();
> +        gen_load_gpr(t1, rt);
> +        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
> +                            ctx->default_tcg_memop_mask);
> +        tcg_temp_free(t1);
> +        break;
> +#if defined(TARGET_MIPS64)
> +    case OPC_GSSDX:
> +        t1 = tcg_temp_new();
> +        gen_load_gpr(t1, rt);
> +        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
> +                            ctx->default_tcg_memop_mask);
> +        tcg_temp_free(t1);
> +        break;
> +#endif
> +    case OPC_GSSWXC1:
> +        fp0 = tcg_temp_new_i32();
> +        gen_load_fpr32(ctx, fp0, rt);
> +        tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
> +                            ctx->default_tcg_memop_mask);
> +        tcg_temp_free_i32(fp0);
> +        break;
> +#if defined(TARGET_MIPS64)
> +    case OPC_GSSDXC1:
> +        t1 = tcg_temp_new();
> +        gen_load_fpr64(ctx, t1, rt);
> +        tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEQ |
> +                            ctx->default_tcg_memop_mask);
> +        tcg_temp_free(t1);
> +        break;
> +#endif
> +    default:
> +        break;
> +    }
> +
> +    tcg_temp_free(t0);
> +}
> +
>  /* Traps */
>  static void gen_trap(DisasContext *ctx, uint32_t opc,
>                       int rs, int rt, int16_t imm)
> @@ -30635,6 +30809,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
>                  /* OPC_JIC, OPC_JIALC */
>                  gen_compute_compact_branch(ctx, op, 0, rt, imm);
>              }
> +        } else if (ctx->insn_flags & ASE_LEXT) {
> +            gen_loongson_lsdc2(ctx, rt, rs, rd);
>          } else {
>              /* OPC_LWC2, OPC_SWC2 */
>              /* COP2: Not implemented. */
> --
> 2.27.0

Re: [PATCH 0/4] Basic TCG Loongson-3A1000 Support

[Aleksandar Markovic]

нед, 14. јун 2020. у 10:03 Jiaxun Yang <jiaxun.yang@flygoat.com> је написао/ла:
>
> This series is the sucessor of
> "target/mips: Add loongson gs464 core" [1].
>

For some reason, patch 4/4 didn't manage to get to the list, and
neither through email. It happens from time to time virtually to
anybody. I guess 4/4 is in a similar form as 3/4. Everything I said
for 3/4 applies to 4/4 as well.

1/4 and 2/4 were applied ti the next mips queue, planned to be sent on
Monday (tomorrow).

Kind regards, and thanks for continuing your contributions!

Aleksandar

> Based on Huacai's CPU define.
> Boot test have been performed with Huacai's KVM series.
>
> Note: This series only adds instructions that can be generated by GCC,
> as we're relying on toolchain for documents of these instructions.
>
> [1]: https://patchwork.kernel.org/cover/11457385/
>
> Thanks.
>
> Jiaxun Yang (4):
>   target/mips: Legalize Loongson insn flags
>   target/mips: Add comments for vendor-specific ASEs
>   target/mips: Add loongson ext lsdc2 instrustions
>   target/mips: Add loongson ext lswc2 instrustions
>
>  target/mips/mips-defs.h |   8 +-
>  target/mips/translate.c | 442 +++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 442 insertions(+), 8 deletions(-)
>
> --
> 2.27.0