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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Huacai Chen , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Jiaxun Yang , QEMU Developers , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" =D1=81=D1=80=D0=B5, 24. =D1=98=D1=83=D0=BD 2020. =D1=83 12:44 Huacai Chen <= zltjiangshi@gmail.com> =D1=98=D0=B5 =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0= =BE/=D0=BB=D0=B0: > > Loongson-3 has an integrated liointc (Local I/O interrupt controller). > It is similar to goldfish interrupt controller, but more powerful (e.g., > it can route external interrupt to multi-cores). > > Documents about Loongson-3's liointc: > 1, https://wiki.godson.ac.cn/ip_block:liointc; > 2, The "I/O=E4=B8=AD=E6=96=AD" section of Loongson-3's user mannual, part= 1. > > Signed-off-by: Huacai Chen > Signed-off-by: Jiaxun Yang > --- Reviewed-by: Aleksandar Markovic > hw/intc/Kconfig | 3 + > hw/intc/Makefile.objs | 1 + > hw/intc/loongson_liointc.c | 241 +++++++++++++++++++++++++++++++++++++++= ++++++ > 3 files changed, 245 insertions(+) > create mode 100644 hw/intc/loongson_liointc.c > > diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig > index f562342..2ae1e89 100644 > --- a/hw/intc/Kconfig > +++ b/hw/intc/Kconfig > @@ -64,3 +64,6 @@ config OMPIC > > config RX_ICU > bool > + > +config LOONGSON_LIOINTC > + bool > diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs > index a420263..3ac2b40 100644 > --- a/hw/intc/Makefile.objs > +++ b/hw/intc/Makefile.objs > @@ -51,3 +51,4 @@ obj-$(CONFIG_MIPS_CPS) +=3D mips_gic.o > obj-$(CONFIG_NIOS2) +=3D nios2_iic.o > obj-$(CONFIG_OMPIC) +=3D ompic.o > obj-$(CONFIG_IBEX) +=3D ibex_plic.o > +obj-$(CONFIG_LOONGSON_LIOINTC) +=3D loongson_liointc.o > diff --git a/hw/intc/loongson_liointc.c b/hw/intc/loongson_liointc.c > new file mode 100644 > index 0000000..e39e39e > --- /dev/null > +++ b/hw/intc/loongson_liointc.c > @@ -0,0 +1,241 @@ > +/* > + * QEMU Loongson Local I/O interrupt controler. > + * > + * Copyright (c) 2020 Jiaxun Yang > + * > + * This program is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "hw/sysbus.h" > +#include "qemu/module.h" > +#include "hw/irq.h" > +#include "hw/qdev-properties.h" > + > +#define D(x) > + > +#define NUM_IRQS 32 > + > +#define NUM_CORES 4 > +#define NUM_IPS 4 > +#define NUM_PARENTS (NUM_CORES * NUM_IPS) > +#define PARENT_COREx_IPy(x, y) (NUM_IPS * x + y) > + > +#define R_MAPPER_START 0x0 > +#define R_MAPPER_END 0x20 > +#define R_ISR R_MAPPER_END > +#define R_IEN 0x24 > +#define R_IEN_SET 0x28 > +#define R_IEN_CLR 0x2c > +#define R_PERCORE_ISR(x) (0x40 + 0x8 * x) > +#define R_END 0x64 > + > +#define TYPE_LOONGSON_LIOINTC "loongson.liointc" > +#define LOONGSON_LIOINTC(obj) \ > + OBJECT_CHECK(struct loongson_liointc, (obj), TYPE_LOONGSON_LIOIN= TC) > + > +struct loongson_liointc { > + SysBusDevice parent_obj; > + > + MemoryRegion mmio; > + qemu_irq parent_irq[NUM_PARENTS]; > + > + uint8_t mapper[NUM_IRQS]; /* 0:3 for core, 4:7 for IP */ > + uint32_t isr; > + uint32_t ien; > + uint32_t per_core_isr[NUM_CORES]; > + > + /* state of the interrupt input pins */ > + uint32_t pin_state; > + bool parent_state[NUM_PARENTS]; > +}; > + > +static void update_irq(struct loongson_liointc *p) > +{ > + uint32_t irq, core, ip; > + uint32_t per_ip_isr[NUM_IPS] =3D {0}; > + > + /* level triggered interrupt */ > + p->isr =3D p->pin_state; > + > + /* Clear disabled IRQs */ > + p->isr &=3D p->ien; > + > + /* Clear per_core_isr */ > + for (core =3D 0; core < NUM_CORES; core++) { > + p->per_core_isr[core] =3D 0; > + } > + > + /* Update per_core_isr and per_ip_isr */ > + for (irq =3D 0; irq < NUM_IRQS; irq++) { > + if (!(p->isr & (1 << irq))) { > + continue; > + } > + > + for (core =3D 0; core < NUM_CORES; core++) { > + if ((p->mapper[irq] & (1 << core))) { > + p->per_core_isr[core] |=3D (1 << irq); > + } > + } > + > + for (ip =3D 0; ip < NUM_IPS; ip++) { > + if ((p->mapper[irq] & (1 << (ip + 4)))) { > + per_ip_isr[ip] |=3D (1 << irq); > + } > + } > + } > + > + /* Emit IRQ to parent! */ > + for (core =3D 0; core < NUM_CORES; core++) { > + for (ip =3D 0; ip < NUM_IPS; ip++) { > + int parent =3D PARENT_COREx_IPy(core, ip); > + if (p->parent_state[parent] !=3D > + (!!p->per_core_isr[core] && !!per_ip_isr[ip])) { > + p->parent_state[parent] =3D !p->parent_state[parent]; > + qemu_set_irq(p->parent_irq[parent], p->parent_state[pare= nt]); > + } > + } > + } > +} > + > +static uint64_t > +liointc_read(void *opaque, hwaddr addr, unsigned int size) > +{ > + struct loongson_liointc *p =3D opaque; > + uint32_t r =3D 0; > + > + /* Mapper is 1 byte */ > + if (size =3D=3D 1 && addr < R_MAPPER_END) { > + r =3D p->mapper[addr]; > + goto out; > + } > + > + /* Rest is 4 byte */ > + if (size !=3D 4 || (addr % 4)) { > + goto out; > + } > + > + if (addr >=3D R_PERCORE_ISR(0) && > + addr < R_PERCORE_ISR(NUM_CORES)) { > + int core =3D (addr - R_PERCORE_ISR(0)) / 4; > + r =3D p->per_core_isr[core]; > + goto out; > + } > + > + switch (addr) { > + case R_ISR: > + r =3D p->isr; > + break; > + case R_IEN: > + r =3D p->ien; > + break; > + default: > + break; > + } > + > +out: > + D(qemu_log("%s: size=3D%d addr=3D%lx val=3D%x\n", __func__, size, ad= dr, r)); > + return r; > +} > + > +static void > +liointc_write(void *opaque, hwaddr addr, > + uint64_t val64, unsigned int size) > +{ > + struct loongson_liointc *p =3D opaque; > + uint32_t value =3D val64; > + > + D(qemu_log("%s: size=3D%d, addr=3D%lx val=3D%x\n", __func__, size, a= ddr, value)); > + > + /* Mapper is 1 byte */ > + if (size =3D=3D 1 && addr < R_MAPPER_END) { > + p->mapper[addr] =3D value; > + goto out; > + } > + > + /* Rest is 4 byte */ > + if (size !=3D 4 || (addr % 4)) { > + goto out; > + } > + > + if (addr >=3D R_PERCORE_ISR(0) && > + addr < R_PERCORE_ISR(NUM_CORES)) { > + int core =3D (addr - R_PERCORE_ISR(0)) / 4; > + p->per_core_isr[core] =3D value; > + goto out; > + } > + > + switch (addr) { > + case R_IEN_SET: > + p->ien |=3D value; > + break; > + case R_IEN_CLR: > + p->ien &=3D ~value; > + break; > + default: > + break; > + } > + > +out: > + update_irq(p); > +} > + > +static const MemoryRegionOps pic_ops =3D { > + .read =3D liointc_read, > + .write =3D liointc_write, > + .endianness =3D DEVICE_NATIVE_ENDIAN, > + .valid =3D { > + .min_access_size =3D 1, > + .max_access_size =3D 4 > + } > +}; > + > +static void irq_handler(void *opaque, int irq, int level) > +{ > + struct loongson_liointc *p =3D opaque; > + > + p->pin_state &=3D ~(1 << irq); > + p->pin_state |=3D level << irq; > + update_irq(p); > +} > + > +static void loongson_liointc_init(Object *obj) > +{ > + struct loongson_liointc *p =3D LOONGSON_LIOINTC(obj); > + int i; > + > + qdev_init_gpio_in(DEVICE(obj), irq_handler, 32); > + > + for (i =3D 0; i < NUM_PARENTS; i++) { > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq[i]); > + } > + > + memory_region_init_io(&p->mmio, obj, &pic_ops, p, > + "loongson.liointc", R_END); > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); > +} > + > +static const TypeInfo loongson_liointc_info =3D { > + .name =3D TYPE_LOONGSON_LIOINTC, > + .parent =3D TYPE_SYS_BUS_DEVICE, > + .instance_size =3D sizeof(struct loongson_liointc), > + .instance_init =3D loongson_liointc_init, > +}; > + > +static void loongson_liointc_register_types(void) > +{ > + type_register_static(&loongson_liointc_info); > +} > + > +type_init(loongson_liointc_register_types) > -- > 2.7.0 >