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X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , QEMU Developers , Huacai Chen , Aleksandar Rikalo , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000e1d03205a23b9cf2 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable 13:23 Uto, 24.03.2020. Jiaxun Yang =D1=98=D0=B5 = =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BE/=D0=BB=D0=B0: > > Loongson multimedia condition instructions were previously implemented as > write 0 to rd due to lack of documentation. So I just confirmed with Loongson > about their encoding and implemented them correctly. > Hi, Jiaxun, Richard Henderson selected your patch to be in his pull request, and the main maintainer, Peter Maydell, accepted it and integrated it into main tree: https://github.com/qemu/qemu/commit/84878f4c00a7beca1d1460e2f77a6c833b8d039= 3#diff-b06d6b84c7a82caf0f5e4645f4b80540 I gather this is your first patch merged in QEMU upstream. Congratulations!! There is a place for you in QEMU community. Hope we hear from you soon, with more fixes, improvements, and new features= . Yours, Aleksandar > Signed-off-by: Jiaxun Yang > Acked-by: Huacai Chen > --- > v1: Use deposit opreations according to Richard's suggestion. > --- > target/mips/translate.c | 35 +++++++++++++++++++++++++++++++---- > 1 file changed, 31 insertions(+), 4 deletions(-) > > diff --git a/target/mips/translate.c b/target/mips/translate.c > index d745bd2803..25b595a17d 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -5529,6 +5529,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) > { > uint32_t opc, shift_max; > TCGv_i64 t0, t1; > + TCGCond cond; > > opc =3D MASK_LMI(ctx->opcode); > switch (opc) { > @@ -5862,14 +5863,39 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) > > case OPC_SEQU_CP2: > case OPC_SEQ_CP2: > + cond =3D TCG_COND_EQ; > + goto do_cc_cond; > + break; > case OPC_SLTU_CP2: > + cond =3D TCG_COND_LTU; > + goto do_cc_cond; > + break; > case OPC_SLT_CP2: > + cond =3D TCG_COND_LT; > + goto do_cc_cond; > + break; > case OPC_SLEU_CP2: > + cond =3D TCG_COND_LEU; > + goto do_cc_cond; > + break; > case OPC_SLE_CP2: > - /* > - * ??? Document is unclear: Set FCC[CC]. Does that mean the > - * FD field is the CC field? > - */ > + cond =3D TCG_COND_LE; > + do_cc_cond: > + { > + int cc =3D (ctx->opcode >> 8) & 0x7; > + TCGv_i64 t64 =3D tcg_temp_new_i64(); > + TCGv_i32 t32 =3D tcg_temp_new_i32(); > + > + tcg_gen_setcond_i64(cond, t64, t0, t1); > + tcg_gen_extrl_i64_i32(t32, t64); > + tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32, > + get_fp_bit(cc), 1); > + > + tcg_temp_free_i32(t32); > + tcg_temp_free_i64(t64); > + } > + goto no_rd; > + break; > default: > MIPS_INVAL("loongson_cp2"); > generate_exception_end(ctx, EXCP_RI); > @@ -5878,6 +5904,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) > > gen_store_fpr64(ctx, t0, rd); > > +no_rd: > tcg_temp_free_i64(t0); > tcg_temp_free_i64(t1); > } > -- > 2.26.0.rc2 > > --000000000000e1d03205a23b9cf2 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

13:23 Uto, 24.03.2020. Jiaxun Yang <jiaxun.yang@flygoat.com> =D1=98=D0=B5 =D0=BD= =D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BE/=D0=BB=D0=B0:
>
> Loongson multimedia condition instructions were previously implemented= as
> write 0 to rd due to lack of documentation. So I just confirmed with L= oongson
> about their encoding and implemented them correctly.
>

Hi, Jiaxun,

Richard Henderson selected your patch to be in his pull requ= est, and the main maintainer, Peter Maydell, accepted it and integrated it = into main tree:

https://= github.com/qemu/qemu/commit/84878f4c00a7beca1d1460e2f77a6c833b8d0393#diff-b= 06d6b84c7a82caf0f5e4645f4b80540

I gather this is your first patch merged in QEMU upstream.

Congratulations!!

There is a place for you in QEMU community.

Hope we hear from you soon, with more fixes, improvements, a= nd new features.

Yours,
Aleksandar

> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Acked-by: Huacai Chen <chenhc@= lemote.com>
> ---
> v1: Use deposit opreations according to Richard's suggestion.
> ---
> =C2=A0target/mips/translate.c | 35 +++++++++++++++++++++++++++++++----=
> =C2=A01 file changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index d745bd2803..25b595a17d 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -5529,6 +5529,7 @@ static void gen_loongson_multimedia(DisasContext= *ctx, int rd, int rs, int rt)
> =C2=A0{
> =C2=A0 =C2=A0 =C2=A0uint32_t opc, shift_max;
> =C2=A0 =C2=A0 =C2=A0TCGv_i64 t0, t1;
> +=C2=A0 =C2=A0 TCGCond cond;
>
> =C2=A0 =C2=A0 =C2=A0opc =3D MASK_LMI(ctx->opcode);
> =C2=A0 =C2=A0 =C2=A0switch (opc) {
> @@ -5862,14 +5863,39 @@ static void gen_loongson_multimedia(DisasConte= xt *ctx, int rd, int rs, int rt)
>
> =C2=A0 =C2=A0 =C2=A0case OPC_SEQU_CP2:
> =C2=A0 =C2=A0 =C2=A0case OPC_SEQ_CP2:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 cond =3D TCG_COND_EQ;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto do_cc_cond;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> =C2=A0 =C2=A0 =C2=A0case OPC_SLTU_CP2:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 cond =3D TCG_COND_LTU;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto do_cc_cond;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> =C2=A0 =C2=A0 =C2=A0case OPC_SLT_CP2:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 cond =3D TCG_COND_LT;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto do_cc_cond;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> =C2=A0 =C2=A0 =C2=A0case OPC_SLEU_CP2:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 cond =3D TCG_COND_LEU;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto do_cc_cond;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> =C2=A0 =C2=A0 =C2=A0case OPC_SLE_CP2:
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* ??? Document is unclear: Set FCC[= CC].=C2=A0 Does that mean the
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* FD field is the CC field?
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 cond =3D TCG_COND_LE;
> +=C2=A0 =C2=A0 do_cc_cond:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int cc =3D (ctx->opcode = >> 8) & 0x7;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv_i64 t64 =3D tcg_temp_n= ew_i64();
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 TCGv_i32 t32 =3D tcg_temp_n= ew_i32();
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_setcond_i64(cond, t= 64, t0, t1);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_extrl_i64_i32(t32, = t64);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_gen_deposit_i32(fpu_fcr= 31, fpu_fcr31, t32,
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 get_fp_bit(cc), 1);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_temp_free_i32(t32);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tcg_temp_free_i64(t64);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto no_rd;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
> =C2=A0 =C2=A0 =C2=A0default:
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MIPS_INVAL("loongson_cp2")= ;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0generate_exception_end(ctx, EXCP_RI)= ;
> @@ -5878,6 +5904,7 @@ static void gen_loongson_multimedia(DisasContext= *ctx, int rd, int rs, int rt)
>
> =C2=A0 =C2=A0 =C2=A0gen_store_fpr64(ctx, t0, rd);
>
> +no_rd:
> =C2=A0 =C2=A0 =C2=A0tcg_temp_free_i64(t0);
> =C2=A0 =C2=A0 =C2=A0tcg_temp_free_i64(t1);
> =C2=A0}
> --
> 2.26.0.rc2
>
>

--000000000000e1d03205a23b9cf2--