[PATCH 0/3] target/mips: Add loongson gs464 core

[PATCH 0/3] target/mips: Add loongson gs464 core

[Jiaxun Yang]

Loongson gs464 core can be found in Loongson-3A1000 processor.
This patchset add minimal support for that core.
There are still some instructions missing, I'm going to work on
them later.

The corresponding hw board is also missing. I'm using modified kernel
for malta for testing purpose and planing to take the design of Lemote's
KVM virtual machine.

Official manual of this core can be found here [1] (In Chinese).
My collection of instruction documents mainly based on Chinese
version of manual, binutils gas code and experiments on real machine
can be found here [2] (In English).

[1]: http://loongson.cn/uploadfile/cpu/3A1000/Loongson_3A1000_cpu_user_2.pdf
[2]: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md

Jiaxun Yang (3):
  target/mips: Introduce loongson ext & mmi ASE flags
  target/mips: Add loongson ext lsdc2 instrustions
  target/mips: Add loongson gs464 core

 target/mips/mips-defs.h          |   2 +
 target/mips/translate.c          | 166 ++++++++++++++++++++++++++++++-
 target/mips/translate_init.inc.c |  25 ++++-
 3 files changed, 188 insertions(+), 5 deletions(-)

-- 
2.26.0.rc2

[PATCH 1/3] target/mips: Introduce loongson ext & mmi ASE flags

[Jiaxun Yang]

Start from Loongson-3A, loongson treat their extension instructions
as ASE and implemented mips64r2 as their baseline ISA.
Here we simply identify instructions shared between 2F and 3A and
mark them with MMI or EXT flag.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/mips/mips-defs.h | 2 ++
 target/mips/translate.c | 9 +++++----
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index a831bb4384..1d25417c76 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -58,6 +58,8 @@
  */
 #define ASE_MMI           0x0100000000000000ULL
 #define ASE_MXU           0x0200000000000000ULL
+#define ASE_LOONGSON_MMI  0x0400000000000000ULL
+#define ASE_LOONGSON_EXT  0x0800000000000000ULL
 
 /* MIPS CPU defines. */
 #define CPU_MIPS1       (ISA_MIPS1)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 25b595a17d..2d556e0dea 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -3421,7 +3421,8 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
     TCGv t0, t1, t2;
     int mem_idx = ctx->mem_idx;
 
-    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
+    if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
+                                        ASE_LOONGSON_EXT)) {
         /*
          * Loongson CPU uses a load to zero register for prefetch.
          * We emulate it as a NOP. On other CPU we must perform the
@@ -27161,7 +27162,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MULTU_G_2F:
     case OPC_MOD_G_2F:
     case OPC_MODU_G_2F:
-        check_insn(ctx, INSN_LOONGSON2F);
+        check_insn(ctx, INSN_LOONGSON2F | ASE_LOONGSON_EXT);
         gen_loongson_integer(ctx, op1, rd, rs, rt);
         break;
     case OPC_CLO:
@@ -27194,7 +27195,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
     case OPC_DDIVU_G_2F:
     case OPC_DMOD_G_2F:
     case OPC_DMODU_G_2F:
-        check_insn(ctx, INSN_LOONGSON2F);
+        check_insn(ctx, INSN_LOONGSON2F | ASE_LOONGSON_EXT);
         gen_loongson_integer(ctx, op1, rd, rs, rt);
         break;
 #endif
@@ -30641,7 +30642,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case OPC_CP2:
-        check_insn(ctx, INSN_LOONGSON2F);
+        check_insn(ctx, INSN_LOONGSON2F | ASE_LOONGSON_MMI);
         /* Note that these instructions use different fields.  */
         gen_loongson_multimedia(ctx, sa, rd, rt);
         break;
-- 
2.26.0.rc2

[PATCH 2/3] target/mips: Add loongson ext lsdc2 instrustions

[Jiaxun Yang]

LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
instructions by loongson-ext ASE.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/mips/translate.c | 157 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 157 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2d556e0dea..255d999f74 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -460,6 +460,24 @@ enum {
     R6_OPC_SCD         = 0x27 | OPC_SPECIAL3,
 };
 
+/* Loongson EXT LDC2/SDC2 opcodes */
+#define MASK_LOONGSON_LSDC2(op)           (MASK_OP_MAJOR(op) | (op & 0x7))
+
+enum {
+    OPC_GSLBX      = 0x0 | OPC_LDC2,
+    OPC_GSLHX      = 0x1 | OPC_LDC2,
+    OPC_GSLWX      = 0x2 | OPC_LDC2,
+    OPC_GSLDX      = 0x3 | OPC_LDC2,
+    OPC_GSLWXC1    = 0x6 | OPC_LDC2,
+    OPC_GSLDXC1    = 0x7 | OPC_LDC2,
+    OPC_GSSBX      = 0x0 | OPC_SDC2,
+    OPC_GSSHX      = 0x1 | OPC_SDC2,
+    OPC_GSSWX      = 0x2 | OPC_SDC2,
+    OPC_GSSDX      = 0x3 | OPC_SDC2,
+    OPC_GSSWXC1    = 0x6 | OPC_SDC2,
+    OPC_GSSDXC1    = 0x7 | OPC_SDC2,
+};
+
 /* BSHFL opcodes */
 #define MASK_BSHFL(op)              (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 
@@ -5910,6 +5928,143 @@ no_rd:
     tcg_temp_free_i64(t1);
 }
 
+/* Loongson EXT LDC2/SDC2 */
+static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
+                                int rs, int rd)
+{
+    int offset = (int8_t)(ctx->opcode >> 3);
+    uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode);
+    TCGv t0, t1;
+    TCGv_i32 t32;
+    TCGv_i64 t64;
+
+    /* Pre-conditions */
+    switch (opc) {
+    case OPC_GSLBX:
+    case OPC_GSLHX:
+    case OPC_GSLWX:
+    case OPC_GSLDX:
+        /* prefetch, implement as NOP */
+        if (rt == 0) {
+            return;
+        }
+        break;
+    case OPC_GSSBX:
+    case OPC_GSSHX:
+    case OPC_GSSWX:
+    case OPC_GSSDX:
+        break;
+    case OPC_GSLWXC1:
+    case OPC_GSLDXC1:
+        check_cp1_enabled(ctx);
+        /* prefetch, implement as NOP */
+        if (rt == 0) {
+            return;
+        }
+        break;
+    case OPC_GSSWXC1:
+    case OPC_GSSDXC1:
+        check_cp1_enabled(ctx);
+        break;
+    default:
+        MIPS_INVAL("loongson_lsdc2");
+        generate_exception_end(ctx, EXCP_RI);
+        return;
+        break;
+    }
+
+    t0 = tcg_temp_new();
+    gen_base_offset_addr(ctx, t0, rs, offset);
+    if (rd != 0) {
+        gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
+    }
+
+    switch (opc) {
+    case OPC_GSLBX:
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
+        gen_store_gpr(t0, rt);
+        break;
+    case OPC_GSLHX:
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, rt);
+        break;
+    case OPC_GSLWX:
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, rt);
+        break;
+#if defined(TARGET_MIPS64)
+    case OPC_GSLDX:
+        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_store_gpr(t0, rt);
+        break;
+#endif
+    case OPC_GSLWXC1:
+        t32 = tcg_temp_new_i32();
+        tcg_gen_qemu_ld_i32(t32, t0, ctx->mem_idx, MO_TESL |
+                            ctx->default_tcg_memop_mask);
+        gen_store_fpr32(ctx, t32, rt);
+        tcg_temp_free_i32(t32);
+        break;
+    case OPC_GSLDXC1:
+        t64 = tcg_temp_new_i64();
+        tcg_gen_qemu_ld_i64(t64, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        gen_store_fpr64(ctx, t64, rt);
+        tcg_temp_free_i64(t64);
+        break;
+    case OPC_GSSBX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB);
+        tcg_temp_free(t1);
+        break;
+    case OPC_GSSHX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+    case OPC_GSSWX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+#if defined(TARGET_MIPS64)
+    case OPC_GSSDX:
+        t1 = tcg_temp_new();
+        gen_load_gpr(t1, rt);
+        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free(t1);
+        break;
+#endif
+    case OPC_GSSWXC1:
+        t32 = tcg_temp_new_i32();
+        gen_load_fpr32(ctx, t32, rt);
+        tcg_gen_qemu_st_i32(t32, t0, ctx->mem_idx, MO_TEUL |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free_i32(t32);
+        break;
+    case OPC_GSSDXC1:
+        t64 = tcg_temp_new_i64();
+        gen_load_fpr64(ctx, t64, rt);
+        tcg_gen_qemu_st_i64(t64, t0, ctx->mem_idx, MO_TEQ |
+                            ctx->default_tcg_memop_mask);
+        tcg_temp_free_i64(t64);
+        break;
+    default:
+        break;
+    }
+
+    tcg_temp_free(t0);
+}
+
 /* Traps */
 static void gen_trap(DisasContext *ctx, uint32_t opc,
                      int rs, int rt, int16_t imm)
@@ -30635,6 +30790,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
                 /* OPC_JIC, OPC_JIALC */
                 gen_compute_compact_branch(ctx, op, 0, rt, imm);
             }
+        } else if (ctx->insn_flags & ASE_LOONGSON_EXT) {
+            gen_loongson_lsdc2(ctx, rt, rs, rd);
         } else {
             /* OPC_LWC2, OPC_SWC2 */
             /* COP2: Not implemented. */
-- 
2.26.0.rc2

[PATCH 3/3] target/mips: Add loongson gs464 core

[Jiaxun Yang]

GS464 is the core we can found in Loongson-3A1000 processor with
MIPS64R2 as baseline ISA and Loongson self defined MMI & EXT ASE.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/mips/translate_init.inc.c | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index 6d145a905a..4e1eb5a2e4 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -830,7 +830,30 @@ const mips_def_t mips_defs[] =
         .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
         .mmu_type = MMU_TYPE_R4000,
     },
-
+    {
+        .name = "gs464",
+        .CP0_PRid = 0x6305,
+        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+                       (MMU_TYPE_R4000 << CP0C0_MT),
+        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+                       (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+                       (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+                       (1 << CP0C1_C2) | (1 << CP0C1_PC) | (1 << CP0C1_EP),
+        .CP0_Config2 = MIPS_CONFIG2 | (1 << CP0C2_SU) | (6 << CP0C2_SU) |
+                        (4 << CP0C2_SU) | (3 << CP0C2_SU),
+        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+        .CP0_PageGrain = (1 << CP0PG_ELPA),
+        .SYNCI_Step = 32,
+        .CCRes = 2,
+        .CP0_Status_rw_bitmask = 0x76FBFFFF,
+        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_PS) | (1 << FCR0_L) |
+                    (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
+                    (0x01 << FCR0_PRID) | (0x1 << FCR0_REV),
+        .SEGBITS = 42,
+        .PABITS = 48,
+        .insn_flags = CPU_MIPS64R2 | ASE_LOONGSON_MMI | ASE_LOONGSON_EXT,
+        .mmu_type = MMU_TYPE_R4000,
+    },
 #endif
 };
 const int mips_defs_number = ARRAY_SIZE(mips_defs);
-- 
2.26.0.rc2

Re: [PATCH 0/3] target/mips: Add loongson gs464 core

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 1545 bytes --]

12:05 Sre, 25.03.2020. Jiaxun Yang <jiaxun.yang@flygoat.com> је написао/ла:
>
> Loongson gs464 core can be found in Loongson-3A1000 processor.
> This patchset add minimal support for that core.
> There are still some instructions missing, I'm going to work on
> them later.
>
> The corresponding hw board is also missing. I'm using modified kernel
> for malta for testing purpose and planing to take the design of Lemote's
> KVM virtual machine.
>
> Official manual of this core can be found here [1] (In Chinese).
> My collection of instruction documents mainly based on Chinese
> version of manual, binutils gas code and experiments on real machine
> can be found here [2] (In English).
>
> [1]:
http://loongson.cn/uploadfile/cpu/3A1000/Loongson_3A1000_cpu_user_2.pdf
> [2]: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
>

Thanks, Jiaxun!

Just to mention whay you probably know, since this is a new feature, this
is too late for 5.0, so we are shooting for integrsying it in 5.1.

Speak to you later of course in more details.

Yours,
Aleksandar

> Jiaxun Yang (3):
>   target/mips: Introduce loongson ext & mmi ASE flags
>   target/mips: Add loongson ext lsdc2 instrustions
>   target/mips: Add loongson gs464 core
>
>  target/mips/mips-defs.h          |   2 +
>  target/mips/translate.c          | 166 ++++++++++++++++++++++++++++++-
>  target/mips/translate_init.inc.c |  25 ++++-
>  3 files changed, 188 insertions(+), 5 deletions(-)
>
> --
> 2.26.0.rc2
>
>

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Re: [PATCH 0/3] target/mips: Add loongson gs464 core

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 2199 bytes --]

00:02 Pet, 27.03.2020. Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
је написао/ла:
>
> 12:05 Sre, 25.03.2020. Jiaxun Yang <jiaxun.yang@flygoat.com> је
написао/ла:
> >
> > Loongson gs464 core can be found in Loongson-3A1000 processor.
> > This patchset add minimal support for that core.
> > There are still some instructions missing, I'm going to work on
> > them later.
> >
> > The corresponding hw board is also missing. I'm using modified kernel
> > for malta for testing purpose and planing to take the design of Lemote's
> > KVM virtual machine.
> >
> > Official manual of this core can be found here [1] (In Chinese).
> > My collection of instruction documents mainly based on Chinese
> > version of manual, binutils gas code and experiments on real machine
> > can be found here [2] (In English).
> >
> > [1]:
http://loongson.cn/uploadfile/cpu/3A1000/Loongson_3A1000_cpu_user_2.pdf
> > [2]:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
> >
>
> Thanks, Jiaxun!
>
> Just to mention whay you probably know, since this is a new feature, this
is too late for 5.0, so we are shooting for integrsying it in 5.1.
>
> Speak to you later of course in more details.
>

Jiaxun, hello again.

May I ask you to provide us the automatic english transl
tion of document [1]?

translate.google.com site has the festure of uploading and translating a
pdf file. Unfortunately, one can't download resulting pdf file. But, there
is a workaround: one can "print" the page to pdf format from the browser.

There may be other ways of automatic translation of pdfs, but the one above
seems pretty reasonable.

Yours,
Aleksandar

> Yours,
> Aleksandar
>
> > Jiaxun Yang (3):
> >   target/mips: Introduce loongson ext & mmi ASE flags
> >   target/mips: Add loongson ext lsdc2 instrustions
> >   target/mips: Add loongson gs464 core
> >
> >  target/mips/mips-defs.h          |   2 +
> >  target/mips/translate.c          | 166 ++++++++++++++++++++++++++++++-
> >  target/mips/translate_init.inc.c |  25 ++++-
> >  3 files changed, 188 insertions(+), 5 deletions(-)
> >
> > --
> > 2.26.0.rc2
> >
> >

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Re: [PATCH 0/3] target/mips: Add loongson gs464 core

[Jiaxun Yang]

[-- Attachment #1: Type: text/plain, Size: 3028 bytes --]


 ---- 在 星期五, 2020-04-03 18:00:31 Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> 撰写 ----
 > 
 > 00:02 Pet, 27.03.2020. Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> је написао/ла:
 > >
 > > 12:05 Sre, 25.03.2020. Jiaxun Yang <jiaxun.yang@flygoat.com> је написао/ла:
 > > >
 > > > Loongson gs464 core can be found in Loongson-3A1000 processor.
 > > > This patchset add minimal support for that core.
 > > > There are still some instructions missing, I'm going to work on
 > > > them later.
 > > >
 > > > The corresponding hw board is also missing. I'm using modified kernel
 > > > for malta for testing purpose and planing to take the design of Lemote's
 > > > KVM virtual machine.
 > > >
 > > > Official manual of this core can be found here [1] (In Chinese).
 > > > My collection of instruction documents mainly based on Chinese
 > > > version of manual, binutils gas code and experiments on real machine
 > > > can be found here [2] (In English).
 > > >
 > > > [1]: http://loongson.cn/uploadfile/cpu/3A1000/Loongson_3A1000_cpu_user_2.pdf
 > > > [2]: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
 > > >
 > >
 > > Thanks, Jiaxun!
 > >
 > > Just to mention whay you probably know, since this is a new feature, this is too late for 5.0, so we are shooting for integrsying it in 5.1.
 > >
 > > Speak to you later of course in more details.
 > >
 > Jiaxun, hello again.
 > May I ask you to provide us the automatic english transl
 > tion of document [1]?
 > translate.google.com site has the festure of uploading and translating a pdf file. Unfortunately, one can't download resulting pdf file. But, there is a workaround: one can "print" the page to pdf format from the browser.
 > There may be other ways of automatic translation of pdfs, but the one above seems pretty reasonable.
 > Yours,
 > Aleksandar

Hi  Aleksandar, 

Machine translated version attached.

It's not very easy to read it as Google Translation don't know much about
computer sciences vocabulary in Chinese.
And the figures are all messed up.
Also, there are some known errata in this manual, some default values of registers
appear to be different from the actual hardware.

If you have any questions about GS464 please ask me and I'll forward them to
Loongson guys. They're not willing to appear on the list but at least they'll respond
my questions.

Thanks!
 --
Jiaxun Yang
 > 
 > 
 > > Yours,
 > > Aleksandar
 > >
 > > > Jiaxun Yang (3):
 > > >   target/mips: Introduce loongson ext & mmi ASE flags
 > > >   target/mips: Add loongson ext lsdc2 instrustions
 > > >   target/mips: Add loongson gs464 core
 > > >
 > > >  target/mips/mips-defs.h          |   2 +
 > > >  target/mips/translate.c          | 166 ++++++++++++++++++++++++++++++-
 > > >  target/mips/translate_init.inc.c |  25 ++++-
 > > >  3 files changed, 188 insertions(+), 5 deletions(-)
 > > >
 > > > -- 
 > > > 2.26.0.rc2
 > > >
 > > >
 > 
 >

[-- Attachment #2: gs464_translation.pdf --]
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Re: [PATCH 0/3] target/mips: Add loongson gs464 core

[Aleksandar Markovic]

[-- Attachment #1: Type: text/plain, Size: 3454 bytes --]

13:37 Pet, 03.04.2020. Jiaxun Yang <jiaxun.yang@flygoat.com> је написао/ла:
>
>
>  ---- 在 星期五, 2020-04-03 18:00:31 Aleksandar Markovic <
aleksandar.qemu.devel@gmail.com> 撰写 ----
>  >
>  > 00:02 Pet, 27.03.2020. Aleksandar Markovic <
aleksandar.qemu.devel@gmail.com> је написао/ла:
>  > >
>  > > 12:05 Sre, 25.03.2020. Jiaxun Yang <jiaxun.yang@flygoat.com> је
написао/ла:
>  > > >
>  > > > Loongson gs464 core can be found in Loongson-3A1000 processor.
>  > > > This patchset add minimal support for that core.
>  > > > There are still some instructions missing, I'm going to work on
>  > > > them later.
>  > > >
>  > > > The corresponding hw board is also missing. I'm using modified
kernel
>  > > > for malta for testing purpose and planing to take the design of
Lemote's
>  > > > KVM virtual machine.
>  > > >
>  > > > Official manual of this core can be found here [1] (In Chinese).
>  > > > My collection of instruction documents mainly based on Chinese
>  > > > version of manual, binutils gas code and experiments on real
machine
>  > > > can be found here [2] (In English).
>  > > >
>  > > > [1]:
http://loongson.cn/uploadfile/cpu/3A1000/Loongson_3A1000_cpu_user_2.pdf
>  > > > [2]:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
>  > > >
>  > >
>  > > Thanks, Jiaxun!
>  > >
>  > > Just to mention whay you probably know, since this is a new feature,
this is too late for 5.0, so we are shooting for integrsying it in 5.1.
>  > >
>  > > Speak to you later of course in more details.
>  > >
>  > Jiaxun, hello again.
>  > May I ask you to provide us the automatic english transl
>  > tion of document [1]?
>  > translate.google.com site has the festure of uploading and translating
a pdf file. Unfortunately, one can't download resulting pdf file. But,
there is a workaround: one can "print" the page to pdf format from the
browser.
>  > There may be other ways of automatic translation of pdfs, but the one
above seems pretty reasonable.
>  > Yours,
>  > Aleksandar
>
> Hi  Aleksandar,
>
> Machine translated version attached.
>
> It's not very easy to read it as Google Translation don't know much about
> computer sciences vocabulary in Chinese.
> And the figures are all messed up.

That is fine, Jiaxin, and, frankly, I did not expect anything better from
automatic Google translation.

Thanks again.

See you later, on the list!

Aleksandar

> Also, there are some known errata in this manual, some default values of
registers
> appear to be different from the actual hardware.
>
> If you have any questions about GS464 please ask me and I'll forward them
to
> Loongson guys. They're not willing to appear on the list but at least
they'll respond
> my questions.
>
> Thanks!
>  --
> Jiaxun Yang
>  >
>  >
>  > > Yours,
>  > > Aleksandar
>  > >
>  > > > Jiaxun Yang (3):
>  > > >   target/mips: Introduce loongson ext & mmi ASE flags
>  > > >   target/mips: Add loongson ext lsdc2 instrustions
>  > > >   target/mips: Add loongson gs464 core
>  > > >
>  > > >  target/mips/mips-defs.h          |   2 +
>  > > >  target/mips/translate.c          | 166
++++++++++++++++++++++++++++++-
>  > > >  target/mips/translate_init.inc.c |  25 ++++-
>  > > >  3 files changed, 188 insertions(+), 5 deletions(-)
>  > > >
>  > > > --
>  > > > 2.26.0.rc2
>  > > >
>  > > >
>  >
>  >

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