From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72E6EC433E0 for ; Tue, 23 Jun 2020 14:51:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2D11320723 for ; Tue, 23 Jun 2020 14:51:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="clp5I5CR" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2D11320723 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:41780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jnkGy-0003yI-FA for qemu-devel@archiver.kernel.org; Tue, 23 Jun 2020 10:51:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jnkG6-0002ps-4A for qemu-devel@nongnu.org; Tue, 23 Jun 2020 10:50:46 -0400 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45464) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jnkG3-0008Ny-6g for qemu-devel@nongnu.org; Tue, 23 Jun 2020 10:50:45 -0400 Received: by mail-wr1-x442.google.com with SMTP id s10so882180wrw.12 for ; Tue, 23 Jun 2020 07:50:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=obyBSk9S8aFRiIXSSr61RgYEc1CJX6CdMCHiatB2VME=; b=clp5I5CRm+t3D6yNBXSWVGj/kMjNWZCW+Ib07SF7gp32ZLoB21hrAAr+YxieY2xTbh 94KcsGxMD9jQDzGQGsOJMh6bnbesrtb6SHMpX1X6Jz8gXj+zJJ7vmiynPsSnzWUkP2sO km8D9nyjhSuki4kjRqtDUo6D1wS+JkRrZdoTUSCz182JumIOLL2L4WAMsnBW/0ST1RMo frjTkJM1zm6iAM6fVbcJVL26LsvNztKlaWwx7T+QxFoy3NjxTdCFBq5YrtqmGwQGbrI+ ALweu6cgtCh9C1/X3HUj/ujV7JeooomfzbSaB7wOAsKo7GKwlMvnbFVQXlGUxcZCjTMp FwUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=obyBSk9S8aFRiIXSSr61RgYEc1CJX6CdMCHiatB2VME=; b=g3SIruDxCqsiYdGBPjlWEF+8S4bMsx7wJvQOymtJIsIHl6tY9ElpqeFimvOY/NbkYX oIcx/eFg4n7rqk10xnqL8n3ONrsMoyWFxWZ1CCVx/RxsNxN2+Nt8wj4utvn1767T55O9 ieqFsox2LDr9hphk94vr7N/QbcdLCVBafNa6FYhfAf/SCGn2/vR59tHZN2uPhCZ9oJVA LWbgDqKiQZX2BQPkc/bVivRYsNdEKJ0X2fJb9/C0iDwQPbcsmsqIPfYPFDp/eBaOaEGI GD1amQHfPcttRGw2+t2rB6w+3hMJTH220yS1/D8qm0SeiHQsy+wIwN62n+IiY9q0jQuB ppeg== X-Gm-Message-State: AOAM530iZUm/xll3riqACeF64v3B8HkfCmKTebQg5fLypux0X1nszZ+A b4mn1XH3Vf3/qcK2ZSCdswoET1caaoMi9fNL15w= X-Google-Smtp-Source: ABdhPJyUZG03m8BUBeMgQldb/I6yzeSUNcHgC3xoVpN0jXeEnaIpkKB6GQ/MRWe5m6GqgIf0XVU7/vAI02QVmKf8jCE= X-Received: by 2002:adf:f885:: with SMTP id u5mr25292176wrp.402.1592923841506; Tue, 23 Jun 2020 07:50:41 -0700 (PDT) MIME-Version: 1.0 References: <1592914438-30317-1-git-send-email-chenhc@lemote.com> <1592914438-30317-3-git-send-email-chenhc@lemote.com> In-Reply-To: <1592914438-30317-3-git-send-email-chenhc@lemote.com> From: Aleksandar Markovic Date: Tue, 23 Jun 2020 16:50:21 +0200 Message-ID: Subject: Re: [PATCH for-5.1 V5 2/4] hw/intc: Add Loongson liointc support To: Huacai Chen Content-Type: multipart/alternative; boundary="000000000000ba316805a8c17b9d" Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Huacai Chen , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , QEMU Developers , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000ba316805a8c17b9d Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =D1=83=D1=82=D0=BE, 23. =D1=98=D1=83=D0=BD 2020. =D1=83 14:13 Huacai Chen <= zltjiangshi@gmail.com> =D1=98=D0=B5 =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BE/=D0=BB=D0=B0: > Loongson-3 has an integrated liointc (Local I/O interrupt controller). > It is similar to goldfish interrupt controller, but more powerful (e.g., > Any pointers to documentation? Thanks, Aleksandar > it can route external interrupt to multi-cores). > > Signed-off-by: Huacai Chen > Signed-off-by: Jiaxun Yang > --- > hw/intc/Kconfig | 3 + > hw/intc/Makefile.objs | 1 + > hw/intc/loongson_liointc.c | 246 > +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 250 insertions(+) > create mode 100644 hw/intc/loongson_liointc.c > > diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig > index a189d6f..264d82d 100644 > --- a/hw/intc/Kconfig > +++ b/hw/intc/Kconfig > @@ -61,3 +61,6 @@ config S390_FLIC_KVM > > config OMPIC > bool > + > +config LOONGSON_LIOINTC > + bool > diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs > index a61e672..9a26fbe 100644 > --- a/hw/intc/Makefile.objs > +++ b/hw/intc/Makefile.objs > @@ -50,3 +50,4 @@ obj-$(CONFIG_MIPS_CPS) +=3D mips_gic.o > obj-$(CONFIG_NIOS2) +=3D nios2_iic.o > obj-$(CONFIG_OMPIC) +=3D ompic.o > obj-$(CONFIG_IBEX) +=3D ibex_plic.o > +obj-$(CONFIG_LOONGSON_LIOINTC) +=3D loongson_liointc.o > diff --git a/hw/intc/loongson_liointc.c b/hw/intc/loongson_liointc.c > new file mode 100644 > index 0000000..d4c1b48 > --- /dev/null > +++ b/hw/intc/loongson_liointc.c > @@ -0,0 +1,246 @@ > +/* > + * QEMU Loongson Local I/O interrupt controler. > + * > + * Copyright (c) 2020 Jiaxun Yang > + * > + * Permission is hereby granted, free of charge, to any person obtaining > a copy > + * of this software and associated documentation files (the "Software"), > to deal > + * in the Software without restriction, including without limitation the > rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or > sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be > included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHA= LL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR > OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALING= S > IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "hw/sysbus.h" > +#include "qemu/module.h" > +#include "hw/irq.h" > +#include "hw/qdev-properties.h" > + > +#define D(x) > + > +#define NUM_IRQS 32 > + > +#define NUM_CORES 4 > +#define NUM_IPS 4 > +#define NUM_PARENTS (NUM_CORES * NUM_IPS) > +#define PARENT_COREx_IPy(x, y) (NUM_IPS * x + y) > + > +#define R_MAPPER_START 0x0 > +#define R_MAPPER_END 0x20 > +#define R_ISR R_MAPPER_END > +#define R_IEN 0x24 > +#define R_IEN_SET 0x28 > +#define R_IEN_CLR 0x2c > +#define R_PERCORE_ISR(x) (0x40 + 0x8 * x) > +#define R_END 0x64 > + > +#define TYPE_LOONGSON_LIOINTC "loongson.liointc" > +#define LOONGSON_LIOINTC(obj) OBJECT_CHECK(struct loongson_liointc, > (obj), TYPE_LOONGSON_LIOINTC) > + > +struct loongson_liointc > +{ > + SysBusDevice parent_obj; > + > + MemoryRegion mmio; > + qemu_irq parent_irq[NUM_PARENTS]; > + > + uint8_t mapper[NUM_IRQS]; /* 0:3 for core, 4:7 for IP */ > + uint32_t isr; > + uint32_t ien; > + uint32_t per_core_isr[NUM_CORES]; > + > + /* state of the interrupt input pins */ > + uint32_t pin_state; > + bool parent_state[NUM_PARENTS]; > +}; > + > +static void update_irq(struct loongson_liointc *p) > +{ > + uint32_t irq, core, ip; > + uint32_t per_ip_isr[NUM_IPS] =3D {0}; > + > + /* level triggered interrupt */ > + p->isr =3D p->pin_state; > + > + /* Clear disabled IRQs */ > + p->isr &=3D p->ien; > + > + /* Clear per_core_isr */ > + for (core =3D 0; core < NUM_CORES; core++) { > + p->per_core_isr[core] =3D 0; > + } > + > + /* Update per_core_isr and per_ip_isr */ > + for (irq =3D 0; irq < NUM_IRQS; irq++) { > + if (!(p->isr & (1 << irq))) { > + continue; > + } > + > + for (core =3D 0; core < NUM_CORES; core++) { > + if ((p->mapper[irq] & (1 << core))) { > + p->per_core_isr[core] |=3D (1 << irq); > + } > + } > + > + for (ip =3D 0; ip < NUM_IPS; ip++) { > + if ((p->mapper[irq] & (1 << (ip + 4)))) { > + per_ip_isr[ip] |=3D (1 << irq); > + } > + } > + } > + > + /* Emit IRQ to parent! */ > + for (core =3D 0; core < NUM_CORES; core++) { > + for (ip =3D 0; ip < NUM_IPS; ip++) { > + int parent =3D PARENT_COREx_IPy(core, ip); > + if (p->parent_state[parent] !=3D > + (!!p->per_core_isr[core] && !!per_ip_isr[ip])) { > + p->parent_state[parent] =3D !p->parent_state[parent]; > + qemu_set_irq(p->parent_irq[parent], > p->parent_state[parent]); > + } > + } > + } > +} > + > +static uint64_t > +liointc_read(void *opaque, hwaddr addr, unsigned int size) > +{ > + struct loongson_liointc *p =3D opaque; > + uint32_t r =3D 0; > + > + /* Mapper is 1 byte */ > + if (size =3D=3D 1 && addr < R_MAPPER_END) { > + r =3D p->mapper[addr]; > + goto out; > + } > + > + /* Rest is 4 byte */ > + if (size !=3D 4 || (addr % 4)) { > + goto out; > + } > + > + if (addr >=3D R_PERCORE_ISR(0) && > + addr < R_PERCORE_ISR(NUM_CORES)) { > + int core =3D (addr - R_PERCORE_ISR(0)) / 4; > + r =3D p->per_core_isr[core]; > + goto out; > + } > + > + switch (addr) { > + case R_ISR: > + r =3D p->isr; > + break; > + case R_IEN: > + r =3D p->ien; > + break; > + default: > + break; > + } > + > +out: > + D(qemu_log("%s: size=3D%d addr=3D%lx val=3D%x\n", __func__, size, ad= dr, r)); > + return r; > +} > + > +static void > +liointc_write(void *opaque, hwaddr addr, > + uint64_t val64, unsigned int size) > +{ > + struct loongson_liointc *p =3D opaque; > + uint32_t value =3D val64; > + > + D(qemu_log("%s: size=3D%d, addr=3D%lx val=3D%x\n", __func__, size, a= ddr, > value)); > + > + /* Mapper is 1 byte */ > + if (size =3D=3D 1 && addr < R_MAPPER_END) { > + p->mapper[addr] =3D value; > + goto out; > + } > + > + /* Rest is 4 byte */ > + if (size !=3D 4 || (addr % 4)) { > + goto out; > + } > + > + if (addr >=3D R_PERCORE_ISR(0) && > + addr < R_PERCORE_ISR(NUM_CORES)) { > + int core =3D (addr - R_PERCORE_ISR(0)) / 4; > + p->per_core_isr[core] =3D value; > + goto out; > + } > + > + switch (addr) { > + case R_IEN_SET: > + p->ien |=3D value; > + break; > + case R_IEN_CLR: > + p->ien &=3D ~value; > + break; > + default: > + break; > + } > + > +out: > + update_irq(p); > +} > + > +static const MemoryRegionOps pic_ops =3D { > + .read =3D liointc_read, > + .write =3D liointc_write, > + .endianness =3D DEVICE_NATIVE_ENDIAN, > + .valid =3D { > + .min_access_size =3D 1, > + .max_access_size =3D 4 > + } > +}; > + > +static void irq_handler(void *opaque, int irq, int level) > +{ > + struct loongson_liointc *p =3D opaque; > + > + p->pin_state &=3D ~(1 << irq); > + p->pin_state |=3D level << irq; > + update_irq(p); > +} > + > +static void loongson_liointc_init(Object *obj) > +{ > + struct loongson_liointc *p =3D LOONGSON_LIOINTC(obj); > + int i; > + > + qdev_init_gpio_in(DEVICE(obj), irq_handler, 32); > + > + for (i =3D 0; i < NUM_PARENTS; i++) { > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq[i]); > + } > + > + memory_region_init_io(&p->mmio, obj, &pic_ops, p, > + "loongson.liointc", R_END); > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); > +} > + > +static const TypeInfo loongson_liointc_info =3D { > + .name =3D TYPE_LOONGSON_LIOINTC, > + .parent =3D TYPE_SYS_BUS_DEVICE, > + .instance_size =3D sizeof(struct loongson_liointc), > + .instance_init =3D loongson_liointc_init, > +}; > + > +static void loongson_liointc_register_types(void) > +{ > + type_register_static(&loongson_liointc_info); > +} > + > +type_init(loongson_liointc_register_types) > -- > 2.7.0 > > --000000000000ba316805a8c17b9d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=D1=83=D1=82=D0=BE, 23. =D1=98=D1=83=D0=BD 2020. =D1=83 14:= 13 Huacai Chen <zltjiangshi@gma= il.com> =D1=98=D0=B5 =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BE/=D0= =BB=D0=B0:
Loong= son-3 has an integrated liointc (Local I/O interrupt controller).
It is similar to goldfish interrupt controller, but more powerful (e.g.,

Any pointers to documentation?
=
Thanks,
Aleksandar

= =C2=A0
it can route external interrupt to multi-cores).

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
=C2=A0hw/intc/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2= =A03 +
=C2=A0hw/intc/Makefile.objs=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A01 +
=C2=A0hw/intc/loongson_liointc.c | 246 ++++++++++++++++++++++++++++++++++++= +++++++++
=C2=A03 files changed, 250 insertions(+)
=C2=A0create mode 100644 hw/intc/loongson_liointc.c

diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index a189d6f..264d82d 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -61,3 +61,6 @@ config S390_FLIC_KVM

=C2=A0config OMPIC
=C2=A0 =C2=A0 =C2=A0bool
+
+config LOONGSON_LIOINTC
+=C2=A0 =C2=A0 bool
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index a61e672..9a26fbe 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -50,3 +50,4 @@ obj-$(CONFIG_MIPS_CPS) +=3D mips_gic.o
=C2=A0obj-$(CONFIG_NIOS2) +=3D nios2_iic.o
=C2=A0obj-$(CONFIG_OMPIC) +=3D ompic.o
=C2=A0obj-$(CONFIG_IBEX) +=3D ibex_plic.o
+obj-$(CONFIG_LOONGSON_LIOINTC) +=3D loongson_liointc.o
diff --git a/hw/intc/loongson_liointc.c b/hw/intc/loongson_liointc.c
new file mode 100644
index 0000000..d4c1b48
--- /dev/null
+++ b/hw/intc/loongson_liointc.c
@@ -0,0 +1,246 @@
+/*
+ * QEMU Loongson Local I/O interrupt controler.
+ *
+ * Copyright (c) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a= copy
+ * of this software and associated documentation files (the "Software= "), to deal
+ * in the Software without restriction, including without limitation the r= ights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll
+ * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included= in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIN= D, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY= ,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL=
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "qemu/module.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+
+#define D(x)
+
+#define NUM_IRQS=C2=A0 =C2=A0 32
+
+#define NUM_CORES=C2=A0 =C2=A04
+#define NUM_IPS=C2=A0 =C2=A0 =C2=A04
+#define NUM_PARENTS (NUM_CORES * NUM_IPS)
+#define PARENT_COREx_IPy(x, y)=C2=A0 =C2=A0 (NUM_IPS * x + y)
+
+#define R_MAPPER_START=C2=A0 =C2=A0 0x0
+#define R_MAPPER_END=C2=A0 =C2=A0 =C2=A0 0x20
+#define R_ISR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0R_MAPPER_END
+#define R_IEN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x24
+#define R_IEN_SET=C2=A0 =C2=A0 =C2=A0 =C2=A00x28
+#define R_IEN_CLR=C2=A0 =C2=A0 =C2=A0 =C2=A00x2c
+#define R_PERCORE_ISR(x) (0x40 + 0x8 * x)
+#define R_END=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x64
+
+#define TYPE_LOONGSON_LIOINTC "loongson.liointc"
+#define LOONGSON_LIOINTC(obj) OBJECT_CHECK(struct loongson_liointc, (obj),= TYPE_LOONGSON_LIOINTC)
+
+struct loongson_liointc
+{
+=C2=A0 =C2=A0 SysBusDevice parent_obj;
+
+=C2=A0 =C2=A0 MemoryRegion mmio;
+=C2=A0 =C2=A0 qemu_irq parent_irq[NUM_PARENTS];
+
+=C2=A0 =C2=A0 uint8_t mapper[NUM_IRQS]; /* 0:3 for core, 4:7 for IP */
+=C2=A0 =C2=A0 uint32_t isr;
+=C2=A0 =C2=A0 uint32_t ien;
+=C2=A0 =C2=A0 uint32_t per_core_isr[NUM_CORES];
+
+=C2=A0 =C2=A0 /* state of the interrupt input pins */
+=C2=A0 =C2=A0 uint32_t pin_state;
+=C2=A0 =C2=A0 bool parent_state[NUM_PARENTS];
+};
+
+static void update_irq(struct loongson_liointc *p)
+{
+=C2=A0 =C2=A0 uint32_t irq, core, ip;
+=C2=A0 =C2=A0 uint32_t per_ip_isr[NUM_IPS] =3D {0};
+
+=C2=A0 =C2=A0 /* level triggered interrupt */
+=C2=A0 =C2=A0 p->isr =3D p->pin_state;
+
+=C2=A0 =C2=A0 /* Clear disabled IRQs */
+=C2=A0 =C2=A0 p->isr &=3D p->ien;
+
+=C2=A0 =C2=A0 /* Clear per_core_isr */
+=C2=A0 =C2=A0 for (core =3D 0; core < NUM_CORES; core++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 p->per_core_isr[core] =3D 0;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Update per_core_isr and per_ip_isr */
+=C2=A0 =C2=A0 for (irq =3D 0; irq < NUM_IRQS; irq++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!(p->isr & (1 << irq))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 continue;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (core =3D 0; core < NUM_CORES; core++) = {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((p->mapper[irq] & (1 = << core))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 p->per_core_isr= [core] |=3D (1 << irq);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (ip =3D 0; ip < NUM_IPS; ip++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if ((p->mapper[irq] & (1 = << (ip + 4)))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 per_ip_isr[ip] |= =3D (1 << irq);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Emit IRQ to parent! */
+=C2=A0 =C2=A0 for (core =3D 0; core < NUM_CORES; core++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (ip =3D 0; ip < NUM_IPS; ip++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int parent =3D PARENT_COREx_IPy(= core, ip);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (p->parent_state[parent] != =3D
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (!!p->per_core_= isr[core] && !!per_ip_isr[ip])) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 p->parent_state= [parent] =3D !p->parent_state[parent];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_set_irq(p->= ;parent_irq[parent], p->parent_state[parent]);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+}
+
+static uint64_t
+liointc_read(void *opaque, hwaddr addr, unsigned int size)
+{
+=C2=A0 =C2=A0 struct loongson_liointc *p =3D opaque;
+=C2=A0 =C2=A0 uint32_t r =3D 0;
+
+=C2=A0 =C2=A0 /* Mapper is 1 byte */
+=C2=A0 =C2=A0 if (size =3D=3D 1 && addr < R_MAPPER_END) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 r =3D p->mapper[addr];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto out;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Rest is 4 byte */
+=C2=A0 =C2=A0 if (size !=3D 4 || (addr % 4)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto out;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 if (addr >=3D R_PERCORE_ISR(0) &&
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 addr < R_PERCORE_ISR(NUM_CORES)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 int core =3D (addr - R_PERCORE_ISR(0)) / 4; +=C2=A0 =C2=A0 =C2=A0 =C2=A0 r =3D p->per_core_isr[core];
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto out;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 switch (addr) {
+=C2=A0 =C2=A0 case R_ISR:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 r =3D p->isr;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case R_IEN:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 r =3D p->ien;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+
+out:
+=C2=A0 =C2=A0 D(qemu_log("%s: size=3D%d addr=3D%lx val=3D%x\n", = __func__, size, addr, r));
+=C2=A0 =C2=A0 return r;
+}
+
+static void
+liointc_write(void *opaque, hwaddr addr,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint64_t val64, unsigned int size)
+{
+=C2=A0 =C2=A0 struct loongson_liointc *p =3D opaque;
+=C2=A0 =C2=A0 uint32_t value =3D val64;
+
+=C2=A0 =C2=A0 D(qemu_log("%s: size=3D%d, addr=3D%lx val=3D%x\n",= __func__, size, addr, value));
+
+=C2=A0 =C2=A0 /* Mapper is 1 byte */
+=C2=A0 =C2=A0 if (size =3D=3D 1 && addr < R_MAPPER_END) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 p->mapper[addr] =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto out;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 /* Rest is 4 byte */
+=C2=A0 =C2=A0 if (size !=3D 4 || (addr % 4)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto out;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 if (addr >=3D R_PERCORE_ISR(0) &&
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 addr < R_PERCORE_ISR(NUM_CORES)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 int core =3D (addr - R_PERCORE_ISR(0)) / 4; +=C2=A0 =C2=A0 =C2=A0 =C2=A0 p->per_core_isr[core] =3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 goto out;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 switch (addr) {
+=C2=A0 =C2=A0 case R_IEN_SET:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 p->ien |=3D value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 case R_IEN_CLR:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 p->ien &=3D ~value;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+
+out:
+=C2=A0 =C2=A0 update_irq(p);
+}
+
+static const MemoryRegionOps pic_ops =3D {
+=C2=A0 =C2=A0 .read =3D liointc_read,
+=C2=A0 =C2=A0 .write =3D liointc_write,
+=C2=A0 =C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN,
+=C2=A0 =C2=A0 .valid =3D {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .min_access_size =3D 1,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 .max_access_size =3D 4
+=C2=A0 =C2=A0 }
+};
+
+static void irq_handler(void *opaque, int irq, int level)
+{
+=C2=A0 =C2=A0 struct loongson_liointc *p =3D opaque;
+
+=C2=A0 =C2=A0 p->pin_state &=3D ~(1 << irq);
+=C2=A0 =C2=A0 p->pin_state |=3D level << irq;
+=C2=A0 =C2=A0 update_irq(p);
+}
+
+static void loongson_liointc_init(Object *obj)
+{
+=C2=A0 =C2=A0 struct loongson_liointc *p =3D LOONGSON_LIOINTC(obj);
+=C2=A0 =C2=A0 int i;
+
+=C2=A0 =C2=A0 qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
+
+=C2=A0 =C2=A0 for (i =3D 0; i < NUM_PARENTS; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 sysbus_init_irq(SYS_BUS_DEVICE(obj), &p-&g= t;parent_irq[i]);
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 memory_region_init_io(&p->mmio, obj, &pic_ops, p,=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0"loongson.liointc", R_END);
+=C2=A0 =C2=A0 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
+}
+
+static const TypeInfo loongson_liointc_info =3D {
+=C2=A0 =C2=A0 .name=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_LOONGSON_LI= OINTC,
+=C2=A0 =C2=A0 .parent=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D TYPE_SYS_BUS_DEVICE,<= br> +=C2=A0 =C2=A0 .instance_size =3D sizeof(struct loongson_liointc),
+=C2=A0 =C2=A0 .instance_init =3D loongson_liointc_init,
+};
+
+static void loongson_liointc_register_types(void)
+{
+=C2=A0 =C2=A0 type_register_static(&loongson_liointc_info);
+}
+
+type_init(loongson_liointc_register_types)
--
2.7.0

--000000000000ba316805a8c17b9d--