From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33635) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZycJv-00077z-AM for qemu-devel@nongnu.org; Tue, 17 Nov 2015 04:13:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZycJu-0004Q2-1Q for qemu-devel@nongnu.org; Tue, 17 Nov 2015 04:12:59 -0500 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]:37354) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZycJt-0004Pq-Nm for qemu-devel@nongnu.org; Tue, 17 Nov 2015 04:12:57 -0500 Received: by wmww144 with SMTP id w144so16053263wmw.0 for ; Tue, 17 Nov 2015 01:12:56 -0800 (PST) MIME-Version: 1.0 From: Francois Baldassari Date: Tue, 17 Nov 2015 01:12:37 -0800 Message-ID: Content-Type: multipart/alternative; boundary=001a114431ac73eca10524b8eed3 Subject: [Qemu-devel] [PATCH] hw/arm_gic: Correctly restore nested irq priority List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org --001a114431ac73eca10524b8eed3 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Upon activating an interrupt, set the corresponding priority bit in the APR/NSAPR registers without touching the currently set bits. In the event of nested interrupts, the GIC will then have the information it needs to restore the priority of the pre-empted interrupt once the higher priority interrupt finishes execution. Signed-off-by: Fran=C3=A7ois Baldassari --- First time submitter here - I tried to follow http://qemu-project.org/Contribute/SubmitAPatch as best I could but do let me know if I missed anything. hw/intc/arm_gic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d71aeb8..13e297d 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq) int bitno =3D preemption_level % 32; if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { - s->nsapr[regno][cpu] &=3D (1 << bitno); + s->nsapr[regno][cpu] |=3D (1 << bitno); } else { - s->apr[regno][cpu] &=3D (1 << bitno); + s->apr[regno][cpu] |=3D (1 << bitno); } s->running_priority[cpu] =3D prio; --=20 2.4.0 --001a114431ac73eca10524b8eed3 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Upon activating an interrupt, set the correspond= ing priority bit in the APR/NSAPR registers without touching the currently = set bits. In the event of nested interrupts, the GIC will then have the inf= ormation it needs to restore the priority of the pre-empted interrupt once = the higher priority interrupt finishes execution.

Signed-off-by: Fra= n=C3=A7ois Baldassari <francois@p= ebble.com>
---
First time submitter here - I tried to fo= llow http://qem= u-project.org/Contribute/SubmitAPatch as best I could but do let me kno= w if I missed anything.

=C2=A0hw/intc/arm_gic.c= | 4 ++--
=C2=A01 file changed, 2 insertions(+), 2 deletions(-)

d= iff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d71aeb8..13e297d= 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -254,9 = +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
= =C2=A0=C2=A0=C2=A0=C2=A0 int bitno =3D preemption_level % 32;
=C2=A0
= =C2=A0=C2=A0=C2=A0=C2=A0 if (gic_has_groups(s) && GIC_TEST_GROUP(ir= q, (1 << cpu))) {
-=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 s-&g= t;nsapr[regno][cpu] &=3D (1 << bitno);
+=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 s->nsapr[regno][cpu] |=3D (1 << bitno);
= =C2=A0=C2=A0=C2=A0=C2=A0 } else {
-=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 s->apr[regno][cpu] &=3D (1 << bitno);
+=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 s->apr[regno][cpu] |=3D (1 << bitno= );
=C2=A0=C2=A0=C2=A0=C2=A0 }
=C2=A0
=C2=A0=C2=A0=C2=A0=C2=A0 s-&g= t;running_priority[cpu] =3D prio;
--
2.4.0


--001a114431ac73eca10524b8eed3--