* [Qemu-devel] [PATCH] hw/arm_gic: Correctly restore nested irq priority
@ 2015-11-17 9:12 Francois Baldassari
2015-11-17 12:11 ` Peter Maydell
0 siblings, 1 reply; 2+ messages in thread
From: Francois Baldassari @ 2015-11-17 9:12 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-arm
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Upon activating an interrupt, set the corresponding priority bit in the
APR/NSAPR registers without touching the currently set bits. In the event
of nested interrupts, the GIC will then have the information it needs to
restore the priority of the pre-empted interrupt once the higher priority
interrupt finishes execution.
Signed-off-by: François Baldassari <francois@pebble.com>
---
First time submitter here - I tried to follow
http://qemu-project.org/Contribute/SubmitAPatch as best I could but do let
me know if I missed anything.
hw/intc/arm_gic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d71aeb8..13e297d 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int
irq)
int bitno = preemption_level % 32;
if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) {
- s->nsapr[regno][cpu] &= (1 << bitno);
+ s->nsapr[regno][cpu] |= (1 << bitno);
} else {
- s->apr[regno][cpu] &= (1 << bitno);
+ s->apr[regno][cpu] |= (1 << bitno);
}
s->running_priority[cpu] = prio;
--
2.4.0
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH] hw/arm_gic: Correctly restore nested irq priority
2015-11-17 9:12 [Qemu-devel] [PATCH] hw/arm_gic: Correctly restore nested irq priority Francois Baldassari
@ 2015-11-17 12:11 ` Peter Maydell
0 siblings, 0 replies; 2+ messages in thread
From: Peter Maydell @ 2015-11-17 12:11 UTC (permalink / raw)
To: Francois Baldassari; +Cc: qemu-arm, QEMU Developers
On 17 November 2015 at 09:12, Francois Baldassari <francois@pebble.com> wrote:
> Upon activating an interrupt, set the corresponding priority bit in the
> APR/NSAPR registers without touching the currently set bits. In the event of
> nested interrupts, the GIC will then have the information it needs to
> restore the priority of the pre-empted interrupt once the higher priority
> interrupt finishes execution.
>
> Signed-off-by: François Baldassari <francois@pebble.com>
> ---
> First time submitter here - I tried to follow
> http://qemu-project.org/Contribute/SubmitAPatch as best I could but do let
> me know if I missed anything.
Oops, thanks for catching this. Your email client unfortunately
seems to have mangled the patch (it has sent it as multipart
mime with HTML and also wrapped long lines), which makes it hard
to handle with automated tools. Since it's a very short patch I've
just fixed it up by hand and applied it to target-arm.next. If
you're thinking about submitting more patches in the future you
might like to look into getting git send-email working.
thanks
-- PMM
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