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Tsirkin" , Richard Henderson , Marcel Apfelbaum , Mark Cave-Ayland , Helge Deller Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::82a; envelope-from=marcandre.lureau@gmail.com; helo=mail-qt1-x82a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi On Mon, Oct 27, 2025 at 9:31=E2=80=AFPM Peter Maydell wrote: > > On Mon, 27 Oct 2025 at 16:54, Philippe Mathieu-Daud=C3=A9 wrote: > > > > In order to have more PCI host bridges to re-use the > > generic pci_host_data_le_ops MemoryRegionOps, add the > > 'config-reg-check-high-bit' property (%true by default). > > > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > > > diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c > > index b5c624e12e8..d6db365e327 100644 > > --- a/hw/pci/pci_host.c > > +++ b/hw/pci/pci_host.c > > @@ -184,8 +184,10 @@ static void pci_host_data_write(void *opaque, hwad= dr addr, > > { > > PCIHostState *s =3D opaque; > > > > - if (s->config_reg & (1u << 31)) > > - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); > > + if (s->config_reg_check_high_bit && !(s->config_reg & (1U << 31)))= { > > + return; > > + } > > + pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); > > } > > > > static uint64_t pci_host_data_read(void *opaque, > > @@ -193,7 +195,7 @@ static uint64_t pci_host_data_read(void *opaque, > > { > > PCIHostState *s =3D opaque; > > > > - if (!(s->config_reg & (1U << 31))) { > > + if (s->config_reg_check_high_bit && !(s->config_reg & (1U << 31)))= { > > return 0xffffffff; > > } > > return pci_data_read(s->bus, s->config_reg | (addr & 3), len); > > @@ -235,6 +237,8 @@ const VMStateDescription vmstate_pcihost =3D { > > }; > > > > static const Property pci_host_properties_common[] =3D { > > + DEFINE_PROP_BOOL("config-reg-check-high-bit", PCIHostState, > > + config_reg_check_high_bit, true), > > I think it might be useful to name and document this > property at a slightly higher level of abstraction. > > Specifically, this code is handling the behaviour of > the CONFIG_ADDRESS register which is part of the PCI > Configuration Access Method (CAM). For x86 the top bit of > CONFIG_ADDRESS is an Enable bit, which must be set to > cause accesses to CONFIG_DATA to actually do something. > For PCI controllers like Dino there is no Enable bit > defined in CONFIG_ADDRESS[*] and CONFIG_DATA accesses always > take effect. > > [*] http://ftp.parisc-linux.org/docs/chips/dino_ers.pdf page 49 > > So perhaps we could call this "config-address-reg-has-enable-bit" ? > > A documentation comment about its purpose and noting that > the expectation is that this is set by the subclass, > not by end-users, might also be helpful. If this shouldn't be tweaked by users and is specific to a device kind, could it be a bool on the PCIHostBridgeClass ? --=20 Marc-Andr=C3=A9 Lureau