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From: "Clément Chigot" <chigot@adacore.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Cc: qemu-devel@nongnu.org, Frederic Konrad <konrad.frederic@yahoo.fr>,
	 Artyom Tarasenko <atar4qemu@gmail.com>,
	Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Subject: Re: [PATCH-for-10.1 3/4] target/sparc: Log unimplemented ASI load/store accesses
Date: Wed, 26 Mar 2025 15:49:05 +0100	[thread overview]
Message-ID: <CAJ307EgiVoC4Aqw6x2n5cU6k-2eH2McV-3SybZYHPf3GWg3FAA@mail.gmail.com> (raw)
In-Reply-To: <20250325123927.74939-4-philmd@linaro.org>

On Tue, Mar 25, 2025 at 1:39 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> When the cache-controller feature is not implemented,
> log potential ASI access as unimplemented.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/sparc/ldst_helper.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
> index b559afc9a94..d4de32d3c48 100644
> --- a/target/sparc/ldst_helper.c
> +++ b/target/sparc/ldst_helper.c
> @@ -600,6 +600,10 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
>          case 0x0C:          /* Leon3 Date Cache config */
>              if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
>                  ret = leon3_cache_control_ld(env, addr, size);
> +            } else {
> +                qemu_log_mask(LOG_UNIMP,
> +                              "%08x: unimplemented access size: %d\n", addr,

This should rather mimic the line in "default", as the issue is not
just the size value.
Same below.

Otherwise,
Reviewed-by: Clément Chigot <chigot@adacore.com>


> +                              size);
>              }
>              break;
>          case 0x01c00a00: /* MXCC control register */
> @@ -816,6 +820,10 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
>          case 0x0C:          /* Leon3 Date Cache config */
>              if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
>                  leon3_cache_control_st(env, addr, val, size);
> +            } else {
> +                qemu_log_mask(LOG_UNIMP,
> +                              "%08x: unimplemented access size: %d\n", addr,
> +                              size);
>              }
>              break;
>
> --
> 2.47.1
>


  reply	other threads:[~2025-03-26 14:50 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-25 12:39 [PATCH-for-10.1 0/4] target/sparc: Spring cleanups around CPU features & LEON3 Philippe Mathieu-Daudé
2025-03-25 12:39 ` [PATCH-for-10.1 1/4] target/sparc: Expose more CPU features Philippe Mathieu-Daudé
2025-03-25 14:11   ` Richard Henderson
2025-03-25 14:43     ` Philippe Mathieu-Daudé
2025-03-25 12:39 ` [PATCH-for-10.1 2/4] target/sparc: Restrict SPARC64 specific features Philippe Mathieu-Daudé
2025-03-25 14:07   ` Richard Henderson
2025-03-25 14:41     ` Philippe Mathieu-Daudé
2025-03-25 12:39 ` [PATCH-for-10.1 3/4] target/sparc: Log unimplemented ASI load/store accesses Philippe Mathieu-Daudé
2025-03-26 14:49   ` Clément Chigot [this message]
2025-03-25 12:39 ` [PATCH-for-10.1 4/4] target/sparc: Move hardware fields from CPUSPARCState to SPARCCPU Philippe Mathieu-Daudé
2025-03-26 14:54   ` Clément Chigot

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