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Thu, 16 Oct 2025 05:37:00 -0700 (PDT) MIME-Version: 1.0 References: <20251014102439.319915-1-peter.maydell@linaro.org> <4b686af261024bad91bf079a098976de@huawei.com> In-Reply-To: From: Salil Mehta Date: Thu, 16 Oct 2025 12:36:48 +0000 X-Gm-Features: AS18NWDX_SDOAbexP8zCHhNxM5YobpavyeanbngiOHPEhZUxIUW3kkHIuf4cDao Message-ID: Subject: Re: [PATCH] hw/intc/arm_gicv3_kvm: Avoid reading ICC_CTLR_EL1 from kernel in cpuif reset To: Peter Maydell Cc: Salil Mehta , "qemu-devel@nongnu.org" , Marc Zyngier Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=salil.mehta@opnsrc.net; helo=mail-oo1-xc31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Oct 16, 2025 at 12:23=E2=80=AFPM Peter Maydell wrote: > > On Thu, 16 Oct 2025 at 13:17, Salil Mehta wrote: > > > > Hi Peter, > > > > > From: qemu-devel-bounces+salil.mehta=3Dhuawei.com@nongnu.org > > devel-bounces+salil.mehta=3Dhuawei.com@nongnu.org> On Behalf Of Peter > > > Maydell > > > Sent: Tuesday, October 14, 2025 11:25 AM > > > To: qemu-devel@nongnu.org > > > Cc: Salil Mehta ; Marc Zyngier > > > Subject: [PATCH] hw/intc/arm_gicv3_kvm: Avoid reading ICC_CTLR_EL1 fr= om > > > kernel in cpuif reset > > > > > > Currently in arm_gicv3_icc_reset() we read the kernel's value of > > > ICC_CTLR_EL1 as part of resetting the CPU interface. This mostly wor= ks, but > > > we're actually breaking an assumption the kernel makes that userspace= only > > > accesses the in-kernel GIC data when the VM is totally paused, which = may > > > not be the case if a single vCPU is being reset. The effect is that = it's possible > > > that the read attempt returns EBUSY. > > > > > > Avoid this by reading the kernel's value of the reset ICC_CTLR_EL1 on= ce in > > > device realize. This brings ICC_CTLR_EL1 into line with the other cpu= if > > > registers, where we assume we know what the kernel is resetting them = to > > > and just update QEMU's data structures in arm_gicv3_icc_reset(). > > > > > > Signed-off-by: Peter Maydell > > > --- > > > I've only tested this fairly lightly, but it seems to work. > > > Salil, does this fix the EBUSY issues you were seeing ? > > > > > > Would you be absorbing this in your tree now or should I make it part > > of the RFC V7 ? > > > > Reviewed-by: Salil Mehta > > Tested-by: Salil Mehta > > Thanks for the testing. I'll pull it into target-arm.next since > it does fix a potential issue with the current codebase. Thanks. I hope you've noticed my earlier reply. There is a potential *future* breakdown condition with this patch. https://lore.kernel.org/qemu-devel/e2b03da8f7514b57aef7d236be1dcb90@huawei.= com/ I assume you've accepted that as a no-risk? Best regards Salil. > > -- PMM