From: Jia Liu <proljc@gmail.com>
To: Max Filippov <jcmvbkbc@gmail.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v5 11/16] target-or32: Add a IIS dummy board
Date: Thu, 21 Jun 2012 00:41:18 +0800 [thread overview]
Message-ID: <CAJBMM-vUYaCu_RZF9UpoxeNWF+5cdPvvby-YNzoXM4zBMDYnVg@mail.gmail.com> (raw)
In-Reply-To: <CAMo8BfK6N_k63FO1MWQcQssMj1Qg4P--rjEHoT=6zhnx9kcLPg@mail.gmail.com>
Hi Max,
On Wed, Jun 20, 2012 at 8:57 PM, Max Filippov <jcmvbkbc@gmail.com> wrote:
> On Wed, Jun 20, 2012 at 1:42 PM, Jia Liu <proljc@gmail.com> wrote:
>> Hi Max,
>>
>> On Wed, Jun 20, 2012 at 2:29 PM, Max Filippov <jcmvbkbc@gmail.com> wrote:
>>> On 06/18/2012 05:02 AM, Jia Liu wrote:
>>>> Add a dummy board for IIS.
>>>>
>>>> Signed-off-by: Jia Liu<proljc@gmail.com>
>>>
>>> [...]
>>>
>>>
>>>> + if (nd_table[0].vlan) {
>>>> + isa_ne2000_init(isa_bus, 0x92000000, 4,&nd_table[0]);
>>>> + }
>>>
>>> I have noticed that the kernel you provided expects OpenCores ethernet
>>> device.
>>> We have a model for it (: You can look at lx60_net_init() in the
>>> hw/xtensa_lx60.c
>>> to see how it may be connected.
>>>
>>
>> Thank you very much for remind me!
>>
>> Is this code OK?
>>
>> static void or1200_net_init(MemoryRegion *address_space,
>> target_phys_addr_t base,
>> target_phys_addr_t buffers,
>> qemu_irq irq, NICInfo *nd)
>> {
>> DeviceState *dev;
>> SysBusDevice *s;
>> MemoryRegion *ram;
>>
>> dev = qdev_create(NULL, "open_eth");
>> qdev_set_nic_properties(dev, nd);
>> qdev_init_nofail(dev);
>>
>> s = sysbus_from_qdev(dev);
>> sysbus_connect_irq(s, 0, irq);
>> memory_region_add_subregion(get_system_memory(), base,
>> sysbus_mmio_get_region(s, 0));
>>
>> ram = g_malloc(sizeof(*ram));
>> memory_region_init_ram(ram, "open_eth.ram", 0x100);
>> vmstate_register_ram_global(ram);
>> memory_region_add_subregion(address_space, buffers, ram);
>> }
>
> You haven't mapped descriptors window. Seems to me it should look like this:
>
> static void or1200_net_init(MemoryRegion *address_space,
> target_phys_addr_t base,
> target_phys_addr_t descriptors,
> qemu_irq irq, NICInfo *nd)
> {
> DeviceState *dev;
> SysBusDevice *s;
>
> dev = qdev_create(NULL, "open_eth");
> qdev_set_nic_properties(dev, nd);
> qdev_init_nofail(dev);
>
> s = sysbus_from_qdev(dev);
> sysbus_connect_irq(s, 0, irq);
> memory_region_add_subregion(address_space, base,
> sysbus_mmio_get_region(s, 0));
> memory_region_add_subregion(address_space, descriptors,
> sysbus_mmio_get_region(s, 1));
> }
>
Thank you very much for the code.
>>
>> if (nd_table[0].vlan) {
>> or1200_net_init(get_system_memory(), 0x92000000,
>> 0x92100000, env->irq[4], nd_table);
>> }
>>
>
> Also I haven't found where 0x92100000 comes from.
> Is there a memory map documentation for this machine?
>
I'm confused about descriptors, I'm not sure whether 0x92100000 is suitable.
I find the code in linux/arch/openrisc/boot/dts/or1ksim.dts
enet0: ethoc@92000000 {
compatible = "opencores,ethmac-rtlsvn338";
reg = <0x92000000 0x100>;
interrupts = <4>;
};
but I'm not sure what value should a pass to target_phys_addr_t
descriptors, that is, I don't know how can I get the address of
descriptors.
Will you please give me more comment about it? I have no idea how to
deal with it.
> --
> Thanks.
> -- Max
Regards,
Jia.
next prev parent reply other threads:[~2012-06-20 16:41 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-18 1:02 [Qemu-devel] [PATCH v5 00/16] QEMU OpenRISC support Jia Liu
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 01/16] target-or32: Add target stubs and cpu support Jia Liu
2012-06-18 18:28 ` Blue Swirl
2012-06-20 7:14 ` Jia Liu
2012-06-21 17:30 ` Blue Swirl
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 02/16] target-or32: Add target machine Jia Liu
2012-06-18 18:24 ` Blue Swirl
2012-06-20 7:19 ` Jia Liu
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 03/16] target-or32: Add MMU support Jia Liu
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 04/16] target-or32: Add interrupt support Jia Liu
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 05/16] target-or32: Add exception support Jia Liu
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 06/16] target-or32: Add int instruction helpers Jia Liu
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 07/16] target-or32: Add float " Jia Liu
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 08/16] target-or32: Add translation routines Jia Liu
2012-06-18 18:40 ` Blue Swirl
2012-06-19 8:05 ` Jia Liu
2012-06-19 18:33 ` Blue Swirl
2012-06-19 23:11 ` Jia Liu
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 09/16] target-or32: Add PIC support Jia Liu
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 10/16] target-or32: Add timer support Jia Liu
2012-06-18 1:02 ` [Qemu-devel] [PATCH v5 11/16] target-or32: Add a IIS dummy board Jia Liu
2012-06-20 6:29 ` Max Filippov
2012-06-20 9:42 ` Jia Liu
2012-06-20 12:57 ` Max Filippov
2012-06-20 16:41 ` Jia Liu [this message]
2012-06-20 20:07 ` Max Filippov
2012-06-20 20:10 ` [Qemu-devel] [PATCH] target-or32: replace NE2000 with OpenCores 10/100 ethernet adapter Max Filippov
2012-06-21 1:54 ` Jia Liu
2012-06-18 1:03 ` [Qemu-devel] [PATCH v5 12/16] target-or32: Add system instructions Jia Liu
2012-06-18 18:58 ` Blue Swirl
2012-06-19 8:02 ` Jia Liu
2012-06-19 18:25 ` Blue Swirl
2012-06-20 0:17 ` Jia Liu
2012-06-18 1:03 ` [Qemu-devel] [PATCH v5 13/16] target-or32: Add gdb stub support Jia Liu
2012-06-18 1:03 ` [Qemu-devel] [PATCH v5 14/16] target-or32: Add linux syscall, signal and termbits Jia Liu
2012-06-18 1:03 ` [Qemu-devel] [PATCH v5 15/16] target-or32: Add linux user support Jia Liu
2012-06-18 1:03 ` [Qemu-devel] [PATCH v5 16/16] target-or32: Add testcases Jia Liu
2012-06-18 19:11 ` [Qemu-devel] [PATCH v5 00/16] QEMU OpenRISC support Blue Swirl
2012-06-20 7:10 ` Jia Liu
2012-06-21 17:24 ` Blue Swirl
2012-06-21 17:28 ` Peter Maydell
2012-06-22 3:16 ` 陳韋任 (Wei-Ren Chen)
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