* [Qemu-devel] How can I distinguish TLB miss in MMU simulation?
@ 2012-01-17 7:51 Zhi-zhou Zhang
2012-01-17 8:29 ` Max Filippov
0 siblings, 1 reply; 4+ messages in thread
From: Zhi-zhou Zhang @ 2012-01-17 7:51 UTC (permalink / raw)
To: qemu-devel
Hi All,
I'm adding a new target to qemu, now, I'm writing mmu simulation, but
it make me confused.
When TLB miss occurred, I can't seperate DTLB miss from ITLB miss.
I implemented it like this from target-xtensa:
if (rw & 2)
HANDLE DTLB MISS
else
HANDLE ITLB MISS
But it didn't work. May I have some suggestions?
Regards,
Zhizhou Zhang
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Qemu-devel] How can I distinguish TLB miss in MMU simulation?
@ 2012-01-17 7:56 Liu
0 siblings, 0 replies; 4+ messages in thread
From: Liu @ 2012-01-17 7:56 UTC (permalink / raw)
To: qemu-devel
Hi All,
I'm adding a new target to qemu, now, I'm writing mmu simulation, but
it make me confused.
When TLB miss occurred, I can't seperate DTLB miss from ITLB miss.
I implemented it like this from target-xtensa:
if (rw & 2)
HANDLE DTLB MISS
else
HANDLE ITLB MISS
But it didn't work. May I have some suggestions?
Regards,
Jia Liu
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] How can I distinguish TLB miss in MMU simulation?
2012-01-17 7:51 Zhi-zhou Zhang
@ 2012-01-17 8:29 ` Max Filippov
2012-01-17 10:52 ` Zhi-zhou Zhang
0 siblings, 1 reply; 4+ messages in thread
From: Max Filippov @ 2012-01-17 8:29 UTC (permalink / raw)
To: Zhi-zhou Zhang; +Cc: qemu-devel
> I'm adding a new target to qemu, now, I'm writing mmu simulation, but
> it make me confused.
>
> When TLB miss occurred, I can't seperate DTLB miss from ITLB miss.
>
> I implemented it like this from target-xtensa:
>
> if (rw & 2)
> HANDLE DTLB MISS
> else
> HANDLE ITLB MISS
I guess that you mean qemu softmmu tlb miss, that results in a call to the
void tlb_fill(CPUState *env, target_ulong vaddr, int is_write, int
mmu_idx, void *retaddr)
'is_write' argument meaning in this call is the following: 0 -- data
read, 1 -- data write, 2 -- instruction read.
So, probably you should swap your DTLB and ITLB handlers.
> But it didn't work. May I have some suggestions?
--
Thanks.
-- Max
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] How can I distinguish TLB miss in MMU simulation?
2012-01-17 8:29 ` Max Filippov
@ 2012-01-17 10:52 ` Zhi-zhou Zhang
0 siblings, 0 replies; 4+ messages in thread
From: Zhi-zhou Zhang @ 2012-01-17 10:52 UTC (permalink / raw)
To: Max Filippov; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 873 bytes --]
On Tue, Jan 17, 2012 at 4:29 PM, Max Filippov <jcmvbkbc@gmail.com> wrote:
> > I'm adding a new target to qemu, now, I'm writing mmu simulation, but
> > it make me confused.
> >
> > When TLB miss occurred, I can't seperate DTLB miss from ITLB miss.
> >
> > I implemented it like this from target-xtensa:
> >
> > if (rw & 2)
> > HANDLE DTLB MISS
> > else
> > HANDLE ITLB MISS
>
> I guess that you mean qemu softmmu tlb miss, that results in a call to the
>
> void tlb_fill(CPUState *env, target_ulong vaddr, int is_write, int
> mmu_idx, void *retaddr)
>
> 'is_write' argument meaning in this call is the following: 0 -- data
> read, 1 -- data write, 2 -- instruction read.
> So, probably you should swap your DTLB and ITLB handlers.
>
> Got it, many thanks.
> > But it didn't work. May I have some suggestions?
>
> --
> Thanks.
> -- Max
>
--
Regards,
Zhizhou Zhang
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^ permalink raw reply [flat|nested] 4+ messages in thread
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