From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6439BC77B6C for ; Fri, 7 Apr 2023 16:34:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkp2G-0004ZK-Of; Fri, 07 Apr 2023 12:34:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkp2F-0004Z4-Qx for qemu-devel@nongnu.org; Fri, 07 Apr 2023 12:33:59 -0400 Received: from mail-yb1-xb2d.google.com ([2607:f8b0:4864:20::b2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkp2E-0001xu-6Y for qemu-devel@nongnu.org; Fri, 07 Apr 2023 12:33:59 -0400 Received: by mail-yb1-xb2d.google.com with SMTP id r187so49493265ybr.6 for ; Fri, 07 Apr 2023 09:33:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680885236; x=1683477236; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=ufuxEPgcFxysP+JOinvhlQiqSzLUh8BMp+Ht6KNFQtw=; b=aB//ljzp0qGunX6QqkSuRP7tcIL7A/c6tnGpJTo5QamR60eqGXvFYknQPFv5MQpRS2 Btr6miQ3QP55iLGCSGrG8BXQN9Q3nt/dJjvQgdLVgc8ZLgg18sH/joU0hxVU4zhwNPUD 4qu6qBktFZPZRoHmANZ5bDZhFzgFOSOzCL6cKs737Mtm8hcAz1T5N4gaCfHqZH/5uSTa ky60qplwOzFpqSOElKOAV070fkvw3lNKLjFAhG30gbx40Y4NMFAjoxxB7NVFjQRgCsPp j/7vHT5+ax8lU7RXOYrUSMGWRvqn2faCMJ+iNOdqRFZ5WK1Jssqh3C5aRoZCgvRGAkPz FPOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680885236; x=1683477236; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ufuxEPgcFxysP+JOinvhlQiqSzLUh8BMp+Ht6KNFQtw=; b=av1Q+7zw9PzCjqZR45Gy3b0np28xqNJlCHAOC1ZprPiUS4dzG831X5sgdztqVXYZbo 1GzXdYuOC5qAjaq8IPqG0aOAkmT4HuewV+qRK/eSbrzhiPV3LcsHOR+Km1QQn9nOgHww X+Wt132+eyCblnOMY8xH0QYm7zKgesoKenZ68qwt4ZVsQyMnZc8KTVeRvR2kI4/3Yatn HUkFZkB2K49nANL9TKynYPi8hkhaoLkKIGc82I9g1zRtqxPLgRvbJU1yYRgxmo3PpyKE nHm0CShDiImackTAEblUDNQuCIvUSYI14qJohx4OjLYSDvMUsIVNwIomy+Xe2mIWeQoY c2iw== X-Gm-Message-State: AAQBX9fetXaoFwIijjLqPU12w6IFP8Aca/WnIw7Ao9PAXFzHVkf2gFyO 21H8uTBhwe9Go4n88GuzMGe+zac1IppjoD+6oz4= X-Google-Smtp-Source: AKy350ZHvJCARISab0nS/2mVtW+ttXx9p/25zItVvOmHf6/xUgZaQ/gb5Q/6ju5qiWNiBSPzBnjJ+EbIY9xxD6UHPLQ= X-Received: by 2002:a25:d10c:0:b0:b79:22d7:95ff with SMTP id i12-20020a25d10c000000b00b7922d795ffmr2095044ybg.2.1680885236696; Fri, 07 Apr 2023 09:33:56 -0700 (PDT) MIME-Version: 1.0 References: <20230407134044.11638-1-pbonzini@redhat.com> In-Reply-To: <20230407134044.11638-1-pbonzini@redhat.com> From: Stefan Hajnoczi Date: Fri, 7 Apr 2023 12:33:45 -0400 Message-ID: Subject: Re: [PATCH] docs: explain effect of smp_read_barrier_depends() on modern architectures To: Paolo Bonzini Cc: qemu-devel , Stefan Hajnoczi Content-Type: multipart/alternative; boundary="00000000000071092505f8c1975a" Received-SPF: pass client-ip=2607:f8b0:4864:20::b2d; envelope-from=stefanha@gmail.com; helo=mail-yb1-xb2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --00000000000071092505f8c1975a Content-Type: text/plain; charset="UTF-8" On Fri, Apr 7, 2023, 09:41 Paolo Bonzini wrote: > The documentation for smp_read_barrier_depends() does not mention the > architectures > for which it is an optimization, for example ARM and PPC. As a result, it > is not > clear to the reader why one would use it. Relegate Alpha to a footnote > together > with other architectures where it is equivalent to smp_rmb(). > > Suggested-by: Stefan Hajnoczi > Signed-off-by: Paolo Bonzini > --- > docs/devel/atomics.rst | 11 +++++++---- > 1 file changed, 7 insertions(+), 4 deletions(-) > Modulo the typo that Peter mentioned: Reviewed-by: Stefan Hajnoczi diff --git a/docs/devel/atomics.rst b/docs/devel/atomics.rst > index 2157d3312956..8f6273c9283e 100644 > --- a/docs/devel/atomics.rst > +++ b/docs/devel/atomics.rst > @@ -201,10 +201,9 @@ They come in six kinds: > retrieves the address to which the second load will be directed), > the processor will guarantee that the first LOAD will appear to happen > before the second with respect to the other components of the system. > - However, this is not always true---for example, it was not true on > - Alpha processors. Whenever this kind of access happens to shared > - memory (that is not protected by a lock), a read barrier is needed, > - and ``smp_read_barrier_depends()`` can be used instead of ``smp_rmb()``. > + Therefore, unlike ``smp_rmb()`` or ``qatomic_load_acquire()``, > + ``smp_read_barrier_depends()`` can be just a compiler barrier on > + weakly-ordered architectures such as ARM or PPC[#]_. > > Note that the first load really has to have a _data_ dependency and not > a control dependency. If the address for the second load is dependent > @@ -212,6 +211,10 @@ They come in six kinds: > than actually loading the address itself, then it's a _control_ > dependency and a full read barrier or better is required. > > +.. [#] The DEC Alpha is an exception, because > ``smp_read_barrier_depends()`` > + needs a processor barrier. On strongly-ordered architectures such > + as x86 or s390, ``smp_rmb()`` and ``qatomic_load_acquire()`` can > + also be a compiler barriers. > > Memory barriers and ``qatomic_load_acquire``/``qatomic_store_release`` are > mostly used when a data structure has one thread that is always a writer > -- > 2.39.2 > > > --00000000000071092505f8c1975a Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Fri, Apr 7, 2023, 09:41 Paolo Bonzini <pbonzini@redhat.com> wrote:
The documentation for smp_read_barrier_depe= nds() does not mention the architectures
for which it is an optimization, for example ARM and PPC.=C2=A0 As a result= , it is not
clear to the reader why one would use it.=C2=A0 Relegate Alpha to a footnot= e together
with other architectures where it is equivalent to smp_rmb().

Suggested-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
=C2=A0docs/devel/atomics.rst | 11 +++++++----
=C2=A01 file changed, 7 insertions(+), 4 deletions(-)

Modulo the typo that P= eter mentioned:

Reviewed= -by: Stefan Hajnoczi <stefanha@re= dhat.com>

diff --git a/docs/devel/atomics.rst b/docs/devel/atomics.rst
index 2157d3312956..8f6273c9283e 100644
--- a/docs/devel/atomics.rst
+++ b/docs/devel/atomics.rst
@@ -201,10 +201,9 @@ They come in six kinds:
=C2=A0 =C2=A0retrieves the address to which the second load will be directe= d),
=C2=A0 =C2=A0the processor will guarantee that the first LOAD will appear t= o happen
=C2=A0 =C2=A0before the second with respect to the other components of the = system.
-=C2=A0 However, this is not always true---for example, it was not true on<= br> -=C2=A0 Alpha processors.=C2=A0 Whenever this kind of access happens to sha= red
-=C2=A0 memory (that is not protected by a lock), a read barrier is needed,=
-=C2=A0 and ``smp_read_barrier_depends()`` can be used instead of ``smp_rmb= ()``.
+=C2=A0 Therefore, unlike ``smp_rmb()`` or ``qatomic_load_acquire()``,
+=C2=A0 ``smp_read_barrier_depends()`` can be just a compiler barrier on +=C2=A0 weakly-ordered architectures such as ARM or PPC[#]_.

=C2=A0 =C2=A0Note that the first load really has to have a _data_ dependenc= y and not
=C2=A0 =C2=A0a control dependency.=C2=A0 If the address for the second load= is dependent
@@ -212,6 +211,10 @@ They come in six kinds:
=C2=A0 =C2=A0than actually loading the address itself, then it's a _con= trol_
=C2=A0 =C2=A0dependency and a full read barrier or better is required.

+.. [#] The DEC Alpha is an exception, because ``smp_read_barrier_depends()= ``
+=C2=A0 =C2=A0needs a processor barrier.=C2=A0 On strongly-ordered architec= tures such
+=C2=A0 =C2=A0as x86 or s390, ``smp_rmb()`` and ``qatomic_load_acquire()`` = can
+=C2=A0 =C2=A0also be a compiler barriers.

=C2=A0Memory barriers and ``qatomic_load_acquire``/``qatomic_store_release`= ` are
=C2=A0mostly used when a data structure has one thread that is always a wri= ter
--
2.39.2


--00000000000071092505f8c1975a--