From: Stefan Hajnoczi <stefanha@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [PULL 00/41] target-arm queue
Date: Tue, 31 Oct 2023 16:51:40 +0900 [thread overview]
Message-ID: <CAJSP0QVHmcmDuaVavQCvs1x=pdfz09HpxDpitSsY_yL2Kgx87g@mail.gmail.com> (raw)
In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org>
On Fri, 27 Oct 2023 at 23:41, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Hi; here's the latest target-arm queue. Mostly this is refactoring
> and cleanup type patches.
Applied, thanks!
Stefan
>
> thanks
> -- PMM
>
> The following changes since commit c60be6e3e38cb36dc66129e757ec4b34152232be:
>
> Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into staging (2023-10-27 09:43:53 +0900)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20231027
>
> for you to fetch changes up to df93de987f423a0ed918c425f5dbd9a25d3c6229:
>
> hw/net/cadence_gem: enforce 32 bits variable size for CRC (2023-10-27 15:27:06 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Correct minor errors in Cortex-A710 definition
> * Implement Neoverse N2 CPU model
> * Refactor feature test functions out into separate header
> * Fix syndrome for FGT traps on ERET
> * Remove 'hw/arm/boot.h' includes from various header files
> * pxa2xx: Refactoring/cleanup
> * Avoid using 'first_cpu' when first ARM CPU is reachable
> * misc/led: LED state is set opposite of what is expected
> * hw/net/cadence_gen: clean up to use FIELD macros
> * hw/net/cadence_gem: perform PHY access on write only
> * hw/net/cadence_gem: enforce 32 bits variable size for CRC
>
> ----------------------------------------------------------------
> Glenn Miles (1):
> misc/led: LED state is set opposite of what is expected
>
> Luc Michel (11):
> hw/net/cadence_gem: use REG32 macro for register definitions
> hw/net/cadence_gem: use FIELD for screening registers
> hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
> hw/net/cadence_gem: use FIELD to describe NWCFG register fields
> hw/net/cadence_gem: use FIELD to describe DMACFG register fields
> hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
> hw/net/cadence_gem: use FIELD to describe IRQ register fields
> hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
> hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
> hw/net/cadence_gem: perform PHY access on write only
> hw/net/cadence_gem: enforce 32 bits variable size for CRC
>
> Peter Maydell (9):
> target/arm: Correct minor errors in Cortex-A710 definition
> target/arm: Implement Neoverse N2 CPU model
> target/arm: Move feature test functions to their own header
> target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together
> target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2
> target/arm: Move ID_AA64ISAR* test functions together
> target/arm: Move ID_AA64PFR* tests together
> target/arm: Move ID_AA64DFR* feature tests together
> target/arm: Fix syndrome for FGT traps on ERET
>
> Philippe Mathieu-Daudé (20):
> hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header
> hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header
> hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header
> hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header
> hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
> hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header
> hw/sd/pxa2xx: Realize sysbus device before accessing it
> hw/sd/pxa2xx: Do not open-code sysbus_create_simple()
> hw/pcmcia/pxa2xx: Realize sysbus device before accessing it
> hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()
> hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()
> hw/intc/pxa2xx: Convert to Resettable interface
> hw/intc/pxa2xx: Pass CPU reference using QOM link property
> hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()
> hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it
> hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable
>
> docs/system/arm/virt.rst | 1 +
> bsd-user/arm/target_arch.h | 1 +
> include/hw/arm/allwinner-a10.h | 1 -
> include/hw/arm/allwinner-h3.h | 1 -
> include/hw/arm/allwinner-r40.h | 1 -
> include/hw/arm/fsl-imx25.h | 1 -
> include/hw/arm/fsl-imx31.h | 1 -
> include/hw/arm/fsl-imx6.h | 1 -
> include/hw/arm/fsl-imx6ul.h | 1 -
> include/hw/arm/fsl-imx7.h | 1 -
> include/hw/arm/pxa.h | 2 -
> include/hw/arm/xlnx-versal.h | 1 -
> include/hw/arm/xlnx-zynqmp.h | 1 -
> linux-user/aarch64/target_prctl.h | 2 +
> target/arm/cpu-features.h | 994 ++++++++++++++++++++++++++++++++++++++
> target/arm/cpu.h | 971 -------------------------------------
> target/arm/internals.h | 1 +
> target/arm/tcg/translate.h | 2 +-
> hw/arm/armv7m.c | 1 +
> hw/arm/bananapi_m2u.c | 3 +-
> hw/arm/cubieboard.c | 1 +
> hw/arm/exynos4_boards.c | 7 +-
> hw/arm/imx25_pdk.c | 1 +
> hw/arm/kzm.c | 1 +
> hw/arm/mcimx6ul-evk.c | 1 +
> hw/arm/mcimx7d-sabre.c | 1 +
> hw/arm/orangepi.c | 3 +-
> hw/arm/pxa2xx.c | 17 +-
> hw/arm/pxa2xx_pic.c | 38 +-
> hw/arm/realview.c | 2 +-
> hw/arm/sabrelite.c | 1 +
> hw/arm/sbsa-ref.c | 1 +
> hw/arm/virt.c | 1 +
> hw/arm/xilinx_zynq.c | 2 +-
> hw/arm/xlnx-versal-virt.c | 1 +
> hw/arm/xlnx-zcu102.c | 1 +
> hw/intc/armv7m_nvic.c | 1 +
> hw/misc/led.c | 2 +-
> hw/net/cadence_gem.c | 884 ++++++++++++++++++---------------
> hw/pcmcia/pxa2xx.c | 15 -
> hw/sd/pxa2xx_mmci.c | 7 +-
> linux-user/aarch64/cpu_loop.c | 1 +
> linux-user/aarch64/signal.c | 1 +
> linux-user/arm/signal.c | 1 +
> linux-user/elfload.c | 4 +
> linux-user/mmap.c | 4 +
> target/arm/arch_dump.c | 1 +
> target/arm/cpu.c | 1 +
> target/arm/cpu64.c | 1 +
> target/arm/debug_helper.c | 1 +
> target/arm/gdbstub.c | 1 +
> target/arm/helper.c | 1 +
> target/arm/kvm64.c | 1 +
> target/arm/machine.c | 1 +
> target/arm/ptw.c | 1 +
> target/arm/tcg/cpu64.c | 115 ++++-
> target/arm/tcg/hflags.c | 1 +
> target/arm/tcg/m_helper.c | 1 +
> target/arm/tcg/op_helper.c | 1 +
> target/arm/tcg/pauth_helper.c | 1 +
> target/arm/tcg/tlb_helper.c | 1 +
> target/arm/tcg/translate-a64.c | 4 +-
> target/arm/vfp_helper.c | 1 +
> 63 files changed, 1702 insertions(+), 1419 deletions(-)
> create mode 100644 target/arm/cpu-features.h
>
next prev parent reply other threads:[~2023-10-31 7:52 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-27 14:39 [PULL 00/41] target-arm queue Peter Maydell
2023-10-27 14:39 ` [PULL 01/41] target/arm: Correct minor errors in Cortex-A710 definition Peter Maydell
2023-10-27 14:39 ` [PULL 02/41] target/arm: Implement Neoverse N2 CPU model Peter Maydell
2023-10-27 14:39 ` [PULL 03/41] target/arm: Move feature test functions to their own header Peter Maydell
2023-10-27 14:39 ` [PULL 04/41] target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together Peter Maydell
2023-10-27 14:39 ` [PULL 05/41] target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2 Peter Maydell
2023-10-27 14:39 ` [PULL 06/41] target/arm: Move ID_AA64ISAR* test functions together Peter Maydell
2023-10-27 14:39 ` [PULL 07/41] target/arm: Move ID_AA64PFR* tests together Peter Maydell
2023-10-27 14:39 ` [PULL 08/41] target/arm: Move ID_AA64DFR* feature " Peter Maydell
2023-10-27 14:39 ` [PULL 09/41] target/arm: Fix syndrome for FGT traps on ERET Peter Maydell
2023-10-27 14:39 ` [PULL 10/41] hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header Peter Maydell
2023-10-27 14:39 ` [PULL 11/41] hw/arm/allwinner-h3: " Peter Maydell
2023-10-27 14:39 ` [PULL 12/41] hw/arm/allwinner-r40: " Peter Maydell
2023-10-27 14:39 ` [PULL 13/41] hw/arm/fsl-imx25: " Peter Maydell
2023-10-27 14:39 ` [PULL 14/41] hw/arm/fsl-imx31: " Peter Maydell
2023-10-27 14:39 ` [PULL 15/41] hw/arm/fsl-imx6: " Peter Maydell
2023-10-27 14:39 ` [PULL 16/41] hw/arm/fsl-imx6ul: " Peter Maydell
2023-10-27 14:39 ` [PULL 17/41] hw/arm/fsl-imx7: " Peter Maydell
2023-10-27 14:39 ` [PULL 18/41] hw/arm/xlnx-versal: " Peter Maydell
2023-10-27 14:39 ` [PULL 19/41] hw/arm/xlnx-zynqmp: " Peter Maydell
2023-10-27 14:39 ` [PULL 20/41] hw/sd/pxa2xx: Realize sysbus device before accessing it Peter Maydell
2023-10-27 14:39 ` [PULL 21/41] hw/sd/pxa2xx: Do not open-code sysbus_create_simple() Peter Maydell
2023-10-27 14:39 ` [PULL 22/41] hw/pcmcia/pxa2xx: Realize sysbus device before accessing it Peter Maydell
2023-10-27 14:39 ` [PULL 23/41] hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple() Peter Maydell
2023-10-27 14:39 ` [PULL 24/41] hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init() Peter Maydell
2023-10-27 14:39 ` [PULL 25/41] hw/intc/pxa2xx: Convert to Resettable interface Peter Maydell
2023-10-27 14:39 ` [PULL 26/41] hw/intc/pxa2xx: Pass CPU reference using QOM link property Peter Maydell
2023-10-27 14:39 ` [PULL 27/41] hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init() Peter Maydell
2023-10-27 14:39 ` [PULL 28/41] hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it Peter Maydell
2023-10-27 14:39 ` [PULL 29/41] hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable Peter Maydell
2023-10-27 14:39 ` [PULL 30/41] misc/led: LED state is set opposite of what is expected Peter Maydell
2023-10-27 14:39 ` [PULL 31/41] hw/net/cadence_gem: use REG32 macro for register definitions Peter Maydell
2023-10-27 14:39 ` [PULL 32/41] hw/net/cadence_gem: use FIELD for screening registers Peter Maydell
2023-10-27 14:39 ` [PULL 33/41] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields Peter Maydell
2023-10-27 14:39 ` [PULL 34/41] hw/net/cadence_gem: use FIELD to describe NWCFG " Peter Maydell
2023-10-27 14:39 ` [PULL 35/41] hw/net/cadence_gem: use FIELD to describe DMACFG " Peter Maydell
2023-10-27 14:39 ` [PULL 36/41] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS " Peter Maydell
2023-10-27 14:39 ` [PULL 37/41] hw/net/cadence_gem: use FIELD to describe IRQ " Peter Maydell
2023-10-27 14:39 ` [PULL 38/41] hw/net/cadence_gem: use FIELD to describe DESCONF6 " Peter Maydell
2023-10-27 14:39 ` [PULL 39/41] hw/net/cadence_gem: use FIELD to describe PHYMNTNC " Peter Maydell
2024-01-19 22:32 ` Guenter Roeck
2024-01-19 22:36 ` Guenter Roeck
2023-10-27 14:39 ` [PULL 40/41] hw/net/cadence_gem: perform PHY access on write only Peter Maydell
2023-10-27 14:39 ` [PULL 41/41] hw/net/cadence_gem: enforce 32 bits variable size for CRC Peter Maydell
2023-10-29 23:15 ` [PULL 00/41] target-arm queue Stefan Hajnoczi
2023-10-30 10:09 ` Peter Maydell
2023-10-30 22:09 ` Stefan Hajnoczi
2023-11-02 11:08 ` Peter Maydell
2023-10-31 7:51 ` Stefan Hajnoczi [this message]
-- strict thread matches above, loose matches on Subject: below --
2025-02-20 16:20 Peter Maydell
2025-02-21 21:02 ` Stefan Hajnoczi
2024-01-11 11:04 Peter Maydell
2024-01-11 15:16 ` Peter Maydell
2020-10-20 15:56 Peter Maydell
2020-10-20 16:36 ` Philippe Mathieu-Daudé
2020-10-20 16:36 ` no-reply
2019-10-22 13:30 Peter Maydell
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