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From: Jim MacArthur <jim.macarthur@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits
Date: Tue, 25 Nov 2025 21:29:58 +0000	[thread overview]
Message-ID: <CAJfKr9W7DuFGkARhSYfT=aumHcZvFbp3pzV0VLxnqaDUn2JQAg@mail.gmail.com> (raw)
In-Reply-To: <87fra38ogg.fsf@draig.linaro.org>

On Mon, 24 Nov 2025 at 15:01, Alex Bennée <alex.bennee@linaro.org> wrote:
> If we instead use this to test for the presence of the feature and then...
>
> > +
> > +    asm("msr " TCR2_EL1 ", %[x0]\n\t"
> > +        "mrs %[x1], " TCR2_EL1 "\n\t"
> > +        : [x1] "=r" (out)
> > +        : [x0] "r" (in));
> > +
> > +    if ((out & feature_mask) == in) {
> > +        ml_printf("OK\n");
> > +        return 0;
> > +    } else {
> > +        ml_printf("FAIL: read value %lx != written value %lx\n",
> > +                  out & feature_mask, in);
> > +        return 1;
> > +    }
>
> extend this part to check the bits are behaving as the feature dictates
> then we can add a second test like this (Makefile.softmmu-target):
>
>   run-asid2-oldcpu: asid2
>           $(call run-test, $<, \
>             $(QEMU) -monitor none -display none \
>                     -chardev file$(COMMA)path=$<.out$(COMMA)id=output \
>                     $(QEMU_OPTS) $<)
>
>   run-asid2-oldcpu: QEMU_OPTS=-M virt -cpu cortex-a72 -display none $(QEMU_BASE_ARGS) -kernel
>
>   EXTRA_RUNS += run-asid2-oldcpu
>
> Although its a bit clunky - one day I'll get around to converting this
> lot to meson.

Good idea, but as far as I can see cortex-a72 doesn't implement
FEAT_TCR2, and nor does anything other than cpu-max, so the write and
read to TCR2_EL1 will be undefined behaviour (and causes an error in
the test). I could (and probably should) add a test for FEAT_TCR2 as
well, but it won't test anything more than my original test covers.

Jim


  reply	other threads:[~2025-11-25 21:31 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-20 12:54 [PATCH v2 0/3] Basic ASID2 Support Jim MacArthur
2025-11-20 12:54 ` [PATCH 1/3] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur
2025-11-24 13:50   ` Alex Bennée
2025-11-24 19:46   ` Richard Henderson
2025-11-20 12:54 ` [PATCH 2/3] target/arm: Enable ASID2 for cpu_max, allow writes to FNG1, FNG0, A2 Jim MacArthur
2025-11-24 13:52   ` Alex Bennée
2025-11-24 19:46   ` Richard Henderson
2025-11-20 12:54 ` [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur
2025-11-24 15:01   ` Alex Bennée
2025-11-25 21:29     ` Jim MacArthur [this message]
2025-11-26 10:31       ` Alex Bennée
  -- strict thread matches above, loose matches on Subject: below --
2025-11-12  9:17 [PATCH 0/3] Basic ASID2 support Jim MacArthur
2025-11-12  9:17 ` [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur
2025-11-15 12:21   ` Richard Henderson

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