From: Jim MacArthur <jim.macarthur@linaro.org>
To: Gustavo Romero <gustavo.romero@linaro.org>
Cc: qemu-devel@nongnu.org, Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [PATCH V4 2/4] target/arm: Allow writes to FNG1, FNG0, A2
Date: Thu, 4 Dec 2025 16:25:01 +0000 [thread overview]
Message-ID: <CAJfKr9XzUw=-n72ozDv=nQTDMkj5VAYHeZjtdtXvJaK0sPPgpQ@mail.gmail.com> (raw)
In-Reply-To: <c2747a88-436d-41bf-8277-b1c10a1aafc5@linaro.org>
On Tue, 2 Dec 2025 at 14:29, Gustavo Romero <gustavo.romero@linaro.org> wrote:
> Afaics, we are not flushing the TLB here like we do for TCR_ELx (in vmsa_tcr_el12_write) before
> we call raw_write(). Since here we could be changing the A2 & friends bits, which can change
> the value of the ASID being using (like the TCR_ELx.A1 bit), I believe we should flush the TLB
> explicitly here like we do in vmsa_tcr_el12_write().
>
> @rth wdyt?
I agree; the guest could reasonably expect TLB entries previously in
use to stop being matched. In any case, I don't imagine flushing the
TLB here will be a significant performance problem. Good spot!
Jim
next prev parent reply other threads:[~2025-12-04 16:25 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 12:00 [PATCH V4 0/4] Basic ASID2 Support Jim MacArthur
2025-12-02 12:00 ` [PATCH V4 1/4] target/arm: Enable ID_AA64MMFR4_EL1 register Jim MacArthur
2025-12-02 14:28 ` Gustavo Romero
2025-12-02 12:00 ` [PATCH V4 2/4] target/arm: Allow writes to FNG1, FNG0, A2 Jim MacArthur
2025-12-02 14:29 ` Gustavo Romero
2025-12-04 16:25 ` Jim MacArthur [this message]
2025-12-02 12:00 ` [PATCH V4 3/4] target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max Jim MacArthur
2025-12-02 14:29 ` Gustavo Romero
2025-12-02 12:00 ` [PATCH V4 4/4] tests: Add test for ASID2 and write/read of feature bits Jim MacArthur
2025-12-02 14:30 ` Gustavo Romero
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