Re: [PATCH 1/3] docs/specs/tpm: document PPI support on ARM64 virt

[Mohammadfaiz Bawa <mbawa@redhat.com>]

On Thu, Mar 26, 2026 at 2:01 AM Stefan Berger <stefanb@linux.ibm.com> wrote:
>
>
>
> On 3/25/26 4:22 PM, Mohamed Mediouni wrote:
> >
> >> On 25. Mar 2026, at 20:31, Stefan Berger <stefanb@linux.ibm.com> wrote:
> >>
> >>
> >> I remember having played around with TPM for QEMU on ARM64 (Raspberry 5(?)) a while ago and had the impression that there was something related to caching that prevented the MMIO interface from working correctly and Peter may have confirmed this back then on IRC .. I am not sure what exactly it was that didn't work correctly when run natively on ARM hardware. It worked well when run in CPU emulation on x86_64 for example. So I am wondering whether there is a minimum requirement for an ARM CPU or ARM CPU features related to caching that someone needs to know about to be able to use TPM TIS successfully? If so, it would probably be good to mention it here as well. If you know.
> >>
> >> Otherwise this looks good to me.
> >
> > Hi,
> >
> > There are two things here:
> >
> > - For Windows guests it’s a bit complicated
> >
> > Windows guests LDP accesses on the TPM register range which doesn’t match ISV=1
>
> oh, yes, right ldp instruction.
>
> > syndrome requirements and needs a workaround in current QEMU.
> >
> > I _think_ the QEMU-side workaround described below went in, which is:
> >
> > If we map the TPM register range as read directly, trap on write to workaround
> > usage of LDP then we hit...
> >
> > - FEAT_S2FWB
> >
> > This is part of Armv8.4 onwards officially* and allows KVM to force a device
> > memory type read to be promoted to write-back.
>  > > That allows the (easiest) workaround for (1) to work.
> >
> > However that’s not the _only_ workaround, you can remove it and include
> > https://patchew.org/QEMU/20260317174740.31674-1-lucaaamaral@gmail.com/ instead.
> >
> > That works fine and removes reliance on FEAT_S2FWB.
> >
> > * some older Arm chips implement equivalent semantics without signalling it, but
> > that might depend on SoC-level integration.
>
>
> It would be good to mention in the docs what the user needs to know
> about CPU requirements, if anything, so that it can actually work. If
> these recent modifications/patches make the TIS work on any processor,
> then there's nothing to mention...
>
> >
> > Thanks,
> > -Mohamed
> >

Thanks Stefan, Mohamed

I wasn't aware of the LDP / S2FWB angle, appreciate the context.

Looking into it, the FEAT_S2FWB requirement is for TPM TIS MMIO access
in general on ARM64 and predates this series. The PPI region we're
adding is RAM-backed (memory_region_init_ram_device_ptr), so it
shouldn't be affected by that issue.
and for our testing we used an Ampere Altra Max M128-30 (Neoverse N1
r3p1, MIDR 0x413fd0c1). TPM TIS works correctly with Windows 11 ARM64
guests with this fix.

Regards,
Faiz