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Thu, 26 Mar 2026 00:28:05 -0700 (PDT) X-Received: by 2002:a05:6820:16a4:b0:67d:2cb:207a with SMTP id 006d021491bc7-67dff5701c6mr3252380eaf.55.1774510085219; Thu, 26 Mar 2026 00:28:05 -0700 (PDT) MIME-Version: 1.0 References: <20260324-tpm-tis-sysbus-ppi-v1-0-e59175210954@redhat.com> <20260324-tpm-tis-sysbus-ppi-v1-1-e59175210954@redhat.com> <07ff064e-bea4-4beb-811a-f5f3485836d6@linux.ibm.com> In-Reply-To: <07ff064e-bea4-4beb-811a-f5f3485836d6@linux.ibm.com> From: Mohammadfaiz Bawa Date: Thu, 26 Mar 2026 12:57:48 +0530 X-Gm-Features: AQROBzByYSjBQi1uP80mfH_YCddiU-SfdoGBt0CPDqgyTHCes9HpLFg4hc9MXuk Message-ID: Subject: Re: [PATCH 1/3] docs/specs/tpm: document PPI support on ARM64 virt To: Stefan Berger Cc: Mohamed Mediouni , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Stefan Berger , Peter Maydell , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Pierrick Bouvier Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.133.124; envelope-from=mbawa@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Mar 26, 2026 at 2:01=E2=80=AFAM Stefan Berger wrote: > > > > On 3/25/26 4:22 PM, Mohamed Mediouni wrote: > > > >> On 25. Mar 2026, at 20:31, Stefan Berger wrote= : > >> > >> > >> I remember having played around with TPM for QEMU on ARM64 (Raspberry = 5(?)) a while ago and had the impression that there was something related t= o caching that prevented the MMIO interface from working correctly and Pete= r may have confirmed this back then on IRC .. I am not sure what exactly it= was that didn't work correctly when run natively on ARM hardware. It worke= d well when run in CPU emulation on x86_64 for example. So I am wondering w= hether there is a minimum requirement for an ARM CPU or ARM CPU features re= lated to caching that someone needs to know about to be able to use TPM TIS= successfully? If so, it would probably be good to mention it here as well.= If you know. > >> > >> Otherwise this looks good to me. > > > > Hi, > > > > There are two things here: > > > > - For Windows guests it=E2=80=99s a bit complicated > > > > Windows guests LDP accesses on the TPM register range which doesn=E2=80= =99t match ISV=3D1 > > oh, yes, right ldp instruction. > > > syndrome requirements and needs a workaround in current QEMU. > > > > I _think_ the QEMU-side workaround described below went in, which is: > > > > If we map the TPM register range as read directly, trap on write to wor= karound > > usage of LDP then we hit... > > > > - FEAT_S2FWB > > > > This is part of Armv8.4 onwards officially* and allows KVM to force a d= evice > > memory type read to be promoted to write-back. > > > That allows the (easiest) workaround for (1) to work. > > > > However that=E2=80=99s not the _only_ workaround, you can remove it and= include > > https://patchew.org/QEMU/20260317174740.31674-1-lucaaamaral@gmail.com/ = instead. > > > > That works fine and removes reliance on FEAT_S2FWB. > > > > * some older Arm chips implement equivalent semantics without signallin= g it, but > > that might depend on SoC-level integration. > > > It would be good to mention in the docs what the user needs to know > about CPU requirements, if anything, so that it can actually work. If > these recent modifications/patches make the TIS work on any processor, > then there's nothing to mention... > > > > > Thanks, > > -Mohamed > > Thanks Stefan, Mohamed I wasn't aware of the LDP / S2FWB angle, appreciate the context. Looking into it, the FEAT_S2FWB requirement is for TPM TIS MMIO access in general on ARM64 and predates this series. The PPI region we're adding is RAM-backed (memory_region_init_ram_device_ptr), so it shouldn't be affected by that issue. and for our testing we used an Ampere Altra Max M128-30 (Neoverse N1 r3p1, MIDR 0x413fd0c1). TPM TIS works correctly with Windows 11 ARM64 guests with this fix. Regards, Faiz