[PATCH 0/3] hw/tpm: add PPI support to tpm-tis-device on ARM64 virt

[PATCH 0/3] hw/tpm: add PPI support to tpm-tis-device on ARM64 virt

[Mohammadfaiz Bawa]

The ARM virt machine's tpm-tis-device lacks Physical Presence Interface
(PPI) support - no _DSM, _STA, or PPI operation regions in the ACPI
namespace. This causes Windows 11 ARM64 guests logs Event ID 15
(tpm.sys) errors after boot repeatedly.

This series documents the change, refactors tpm_build_ppi_acpi() to
accept a dynamic PPI base address, then wires up PPI MMIO and ACPI
on tpm-tis-sysbus via the platform bus.

Tested: aarch64 KVM, upstream QEMU, Win11 ARM64 25H2, swtpm.
Event ID 15 eliminated.

Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>
---
Mohammadfaiz Bawa (3):
      docs/specs/tpm: document PPI support on ARM64 virt
      hw/acpi/tpm: parameterize PPI base address in tpm_build_ppi_acpi
      hw/tpm: add PPI support to tpm-tis-device for ARM64 virt

 docs/specs/tpm.rst       | 24 ++++++++++++++++++++++++
 hw/acpi/tpm.c            |  8 ++++----
 hw/arm/virt-acpi-build.c |  9 ++++++++-
 hw/tpm/tpm_tis_isa.c     |  2 +-
 hw/tpm/tpm_tis_sysbus.c  | 11 +++++++++++
 include/hw/acpi/tpm.h    |  3 ++-
 6 files changed, 50 insertions(+), 7 deletions(-)
---
base-commit: 8e711856d7639cbffa51405f2cc2366e3d9e3a23
change-id: 20260324-tpm-tis-sysbus-ppi-ef31a7d71753

Best regards,
-- 
Mohammadfaiz Bawa <mbawa@redhat.com>

[PATCH 1/3] docs/specs/tpm: document PPI support on ARM64 virt

[Mohammadfaiz Bawa]

Document that tpm-tis-device on the ARM virt machine supports PPI
with dynamically allocated MMIO via the platform bus, unlike x86
where PPI is at the fixed address 0xFED45000.

Also add hw/arm/virt-acpi-build.c and hw/acpi/tpm.c to the list
of files related to TPM ACPI tables.

Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>
---
 docs/specs/tpm.rst | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst
index b630a351b4f77a8d2512f22446d00a4d674c7777..63cc0b68cd79d64138d4dd05ae158430c6a74643 100644
--- a/docs/specs/tpm.rst
+++ b/docs/specs/tpm.rst
@@ -187,8 +187,30 @@ The location of the table is given by the fw_cfg ``tpmppi_address``
 field.  The PPI memory region size is 0x400 (``TPM_PPI_ADDR_SIZE``) to
 leave enough room for future updates.
 
+PPI on ARM64 virt
+-----------------
+
+The ARM virt machine supports PPI for ``tpm-tis-device`` as defined
+in the `PPI specification`_.
+
+Unlike the x86 TIS device where the PPI memory region is mapped at
+the fixed address ``0xFED45000`` (within the TIS MMIO range), the
+ARM64 sysbus device registers PPI memory as a second MMIO region
+on the platform bus. The platform bus assigns the guest physical
+address dynamically at device plug time. The ACPI ``_DSM`` method
+and PPI operation regions reference this dynamically resolved
+address.
+
+PPI is enabled by default and can be controlled with the ``ppi``
+property (e.g. ``-device tpm-tis-device,tpmdev=tpm0,ppi=on``).
+Without PPI support, guest operating systems such as Windows 11
+ARM64 will log errors when attempting to query TPM Physical
+Presence capabilities via the ACPI ``_DSM`` method.
+
 QEMU files related to TPM ACPI tables:
  - ``hw/i386/acpi-build.c``
+ - ``hw/arm/virt-acpi-build.c``
+ - ``hw/acpi/tpm.c``
  - ``include/hw/acpi/tpm.h``
 
 TPM backend devices

-- 
2.53.0

Re: [PATCH 1/3] docs/specs/tpm: document PPI support on ARM64 virt

[Stefan Berger]

On 3/24/26 3:10 AM, Mohammadfaiz Bawa wrote:
> Document that tpm-tis-device on the ARM virt machine supports PPI
> with dynamically allocated MMIO via the platform bus, unlike x86
> where PPI is at the fixed address 0xFED45000.
> 
> Also add hw/arm/virt-acpi-build.c and hw/acpi/tpm.c to the list
> of files related to TPM ACPI tables.
> 
> Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>
> ---
>   docs/specs/tpm.rst | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst
> index b630a351b4f77a8d2512f22446d00a4d674c7777..63cc0b68cd79d64138d4dd05ae158430c6a74643 100644
> --- a/docs/specs/tpm.rst
> +++ b/docs/specs/tpm.rst
> @@ -187,8 +187,30 @@ The location of the table is given by the fw_cfg ``tpmppi_address``
>   field.  The PPI memory region size is 0x400 (``TPM_PPI_ADDR_SIZE``) to
>   leave enough room for future updates.
> 
> +PPI on ARM64 virt
> +-----------------
> +
> +The ARM virt machine supports PPI for ``tpm-tis-device`` as defined
> +in the `PPI specification`_.
> +
> +Unlike the x86 TIS device where the PPI memory region is mapped at
> +the fixed address ``0xFED45000`` (within the TIS MMIO range), the
> +ARM64 sysbus device registers PPI memory as a second MMIO region
> +on the platform bus. The platform bus assigns the guest physical
> +address dynamically at device plug time. The ACPI ``_DSM`` method
> +and PPI operation regions reference this dynamically resolved
> +address.
> +
> +PPI is enabled by default and can be controlled with the ``ppi``
> +property (e.g. ``-device tpm-tis-device,tpmdev=tpm0,ppi=on``).
> +Without PPI support, guest operating systems such as Windows 11
> +ARM64 will log errors when attempting to query TPM Physical
> +Presence capabilities via the ACPI ``_DSM`` method.

I remember having played around with TPM for QEMU on ARM64 (Raspberry 
5(?)) a while ago and had the impression that there was something 
related to caching that prevented the MMIO interface from working 
correctly and Peter may have confirmed this back then on IRC .. I am not 
sure what exactly it was that didn't work correctly when run natively on 
ARM hardware. It worked well when run in CPU emulation on x86_64 for 
example. So I am wondering whether there is a minimum requirement for an 
ARM CPU or ARM CPU features related to caching that someone needs to 
know about to be able to use TPM TIS successfully? If so, it would 
probably be good to mention it here as well. If you know.

Otherwise this looks good to me.

> +
>   QEMU files related to TPM ACPI tables:
>    - ``hw/i386/acpi-build.c``
> + - ``hw/arm/virt-acpi-build.c``
> + - ``hw/acpi/tpm.c``
>    - ``include/hw/acpi/tpm.h``
> 
>   TPM backend devices
> 

Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>

Re: [PATCH 1/3] docs/specs/tpm: document PPI support on ARM64 virt

[Mohamed Mediouni]

> On 25. Mar 2026, at 20:31, Stefan Berger <stefanb@linux.ibm.com> wrote:
> 
> 
> I remember having played around with TPM for QEMU on ARM64 (Raspberry 5(?)) a while ago and had the impression that there was something related to caching that prevented the MMIO interface from working correctly and Peter may have confirmed this back then on IRC .. I am not sure what exactly it was that didn't work correctly when run natively on ARM hardware. It worked well when run in CPU emulation on x86_64 for example. So I am wondering whether there is a minimum requirement for an ARM CPU or ARM CPU features related to caching that someone needs to know about to be able to use TPM TIS successfully? If so, it would probably be good to mention it here as well. If you know.
> 
> Otherwise this looks good to me.

Hi,

There are two things here:

- For Windows guests it’s a bit complicated

Windows guests LDP accesses on the TPM register range which doesn’t match ISV=1 
syndrome requirements and needs a workaround in current QEMU.

I _think_ the QEMU-side workaround described below went in, which is:

If we map the TPM register range as read directly, trap on write to workaround 
usage of LDP then we hit...

- FEAT_S2FWB

This is part of Armv8.4 onwards officially* and allows KVM to force a device 
memory type read to be promoted to write-back.

That allows the (easiest) workaround for (1) to work.

However that’s not the _only_ workaround, you can remove it and include
https://patchew.org/QEMU/20260317174740.31674-1-lucaaamaral@gmail.com/ instead.

That works fine and removes reliance on FEAT_S2FWB.

* some older Arm chips implement equivalent semantics without signalling it, but
that might depend on SoC-level integration.

Thanks,
-Mohamed

Re: [PATCH 1/3] docs/specs/tpm: document PPI support on ARM64 virt

[Stefan Berger]

On 3/25/26 4:22 PM, Mohamed Mediouni wrote:
> 
>> On 25. Mar 2026, at 20:31, Stefan Berger <stefanb@linux.ibm.com> wrote:
>>
>>
>> I remember having played around with TPM for QEMU on ARM64 (Raspberry 5(?)) a while ago and had the impression that there was something related to caching that prevented the MMIO interface from working correctly and Peter may have confirmed this back then on IRC .. I am not sure what exactly it was that didn't work correctly when run natively on ARM hardware. It worked well when run in CPU emulation on x86_64 for example. So I am wondering whether there is a minimum requirement for an ARM CPU or ARM CPU features related to caching that someone needs to know about to be able to use TPM TIS successfully? If so, it would probably be good to mention it here as well. If you know.
>>
>> Otherwise this looks good to me.
> 
> Hi,
> 
> There are two things here:
> 
> - For Windows guests it’s a bit complicated
> 
> Windows guests LDP accesses on the TPM register range which doesn’t match ISV=1

oh, yes, right ldp instruction.

> syndrome requirements and needs a workaround in current QEMU.
> 
> I _think_ the QEMU-side workaround described below went in, which is:
> 
> If we map the TPM register range as read directly, trap on write to workaround
> usage of LDP then we hit...
> 
> - FEAT_S2FWB
> 
> This is part of Armv8.4 onwards officially* and allows KVM to force a device
> memory type read to be promoted to write-back.
 > > That allows the (easiest) workaround for (1) to work.
> 
> However that’s not the _only_ workaround, you can remove it and include
> https://patchew.org/QEMU/20260317174740.31674-1-lucaaamaral@gmail.com/ instead.
> 
> That works fine and removes reliance on FEAT_S2FWB.
> 
> * some older Arm chips implement equivalent semantics without signalling it, but
> that might depend on SoC-level integration.


It would be good to mention in the docs what the user needs to know 
about CPU requirements, if anything, so that it can actually work. If 
these recent modifications/patches make the TIS work on any processor, 
then there's nothing to mention...

> 
> Thanks,
> -Mohamed
> 
> 
> 

Re: [PATCH 1/3] docs/specs/tpm: document PPI support on ARM64 virt

[Mohammadfaiz Bawa]

On Thu, Mar 26, 2026 at 2:01 AM Stefan Berger <stefanb@linux.ibm.com> wrote:
>
>
>
> On 3/25/26 4:22 PM, Mohamed Mediouni wrote:
> >
> >> On 25. Mar 2026, at 20:31, Stefan Berger <stefanb@linux.ibm.com> wrote:
> >>
> >>
> >> I remember having played around with TPM for QEMU on ARM64 (Raspberry 5(?)) a while ago and had the impression that there was something related to caching that prevented the MMIO interface from working correctly and Peter may have confirmed this back then on IRC .. I am not sure what exactly it was that didn't work correctly when run natively on ARM hardware. It worked well when run in CPU emulation on x86_64 for example. So I am wondering whether there is a minimum requirement for an ARM CPU or ARM CPU features related to caching that someone needs to know about to be able to use TPM TIS successfully? If so, it would probably be good to mention it here as well. If you know.
> >>
> >> Otherwise this looks good to me.
> >
> > Hi,
> >
> > There are two things here:
> >
> > - For Windows guests it’s a bit complicated
> >
> > Windows guests LDP accesses on the TPM register range which doesn’t match ISV=1
>
> oh, yes, right ldp instruction.
>
> > syndrome requirements and needs a workaround in current QEMU.
> >
> > I _think_ the QEMU-side workaround described below went in, which is:
> >
> > If we map the TPM register range as read directly, trap on write to workaround
> > usage of LDP then we hit...
> >
> > - FEAT_S2FWB
> >
> > This is part of Armv8.4 onwards officially* and allows KVM to force a device
> > memory type read to be promoted to write-back.
>  > > That allows the (easiest) workaround for (1) to work.
> >
> > However that’s not the _only_ workaround, you can remove it and include
> > https://patchew.org/QEMU/20260317174740.31674-1-lucaaamaral@gmail.com/ instead.
> >
> > That works fine and removes reliance on FEAT_S2FWB.
> >
> > * some older Arm chips implement equivalent semantics without signalling it, but
> > that might depend on SoC-level integration.
>
>
> It would be good to mention in the docs what the user needs to know
> about CPU requirements, if anything, so that it can actually work. If
> these recent modifications/patches make the TIS work on any processor,
> then there's nothing to mention...
>
> >
> > Thanks,
> > -Mohamed
> >

Thanks Stefan, Mohamed

I wasn't aware of the LDP / S2FWB angle, appreciate the context.

Looking into it, the FEAT_S2FWB requirement is for TPM TIS MMIO access
in general on ARM64 and predates this series. The PPI region we're
adding is RAM-backed (memory_region_init_ram_device_ptr), so it
shouldn't be affected by that issue.
and for our testing we used an Ampere Altra Max M128-30 (Neoverse N1
r3p1, MIDR 0x413fd0c1). TPM TIS works correctly with Windows 11 ARM64
guests with this fix.

Regards,
Faiz

Re: [PATCH 1/3] docs/specs/tpm: document PPI support on ARM64 virt

[Mohamed Mediouni]

> On 26. Mar 2026, at 08:27, Mohammadfaiz Bawa <mbawa@redhat.com> wrote:
> 
> On Thu, Mar 26, 2026 at 2:01 AM Stefan Berger <stefanb@linux.ibm.com> wrote:
>> 
>> 
>> 
>> On 3/25/26 4:22 PM, Mohamed Mediouni wrote:
>>> 
>>>> On 25. Mar 2026, at 20:31, Stefan Berger <stefanb@linux.ibm.com> wrote:
>>>> 
>>>> 
>>>> I remember having played around with TPM for QEMU on ARM64 (Raspberry 5(?)) a while ago and had the impression that there was something related to caching that prevented the MMIO interface from working correctly and Peter may have confirmed this back then on IRC .. I am not sure what exactly it was that didn't work correctly when run natively on ARM hardware. It worked well when run in CPU emulation on x86_64 for example. So I am wondering whether there is a minimum requirement for an ARM CPU or ARM CPU features related to caching that someone needs to know about to be able to use TPM TIS successfully? If so, it would probably be good to mention it here as well. If you know.
>>>> 
>>>> Otherwise this looks good to me.
>>> 
>>> Hi,
>>> 
>>> There are two things here:
>>> 
>>> - For Windows guests it’s a bit complicated
>>> 
>>> Windows guests LDP accesses on the TPM register range which doesn’t match ISV=1
>> 
>> oh, yes, right ldp instruction.
>> 
>>> syndrome requirements and needs a workaround in current QEMU.
>>> 
>>> I _think_ the QEMU-side workaround described below went in, which is:
>>> 
>>> If we map the TPM register range as read directly, trap on write to workaround
>>> usage of LDP then we hit...
>>> 
>>> - FEAT_S2FWB
>>> 
>>> This is part of Armv8.4 onwards officially* and allows KVM to force a device
>>> memory type read to be promoted to write-back.
>>>> That allows the (easiest) workaround for (1) to work.
>>> 
>>> However that’s not the _only_ workaround, you can remove it and include
>>> https://patchew.org/QEMU/20260317174740.31674-1-lucaaamaral@gmail.com/ instead.
>>> 
>>> That works fine and removes reliance on FEAT_S2FWB.
>>> 
>>> * some older Arm chips implement equivalent semantics without signalling it, but
>>> that might depend on SoC-level integration.
>> 
>> 
>> It would be good to mention in the docs what the user needs to know
>> about CPU requirements, if anything, so that it can actually work. If
>> these recent modifications/patches make the TIS work on any processor,
>> then there's nothing to mention...
>> 
>>> 
>>> Thanks,
>>> -Mohamed
>>> 
> 
> Thanks Stefan, Mohamed
> 
> I wasn't aware of the LDP / S2FWB angle, appreciate the context.
> 
Hello,

> Looking into it, the FEAT_S2FWB requirement is for TPM TIS MMIO access
> in general on ARM64 and predates this series.

Yes, it was added as a workaround for baseline Windows support.

> The PPI region we're
> adding is RAM-backed (memory_region_init_ram_device_ptr), so it
> shouldn't be affected by that issue.

FEAT_S2FWB is for the case where the guest tries to access as MMIO
while the memory region is RAM-backed.

From a quick look at the Linux kernel driver it does a
devm_ioremap_resource which assumes MMIO in drivers/char/tpm/tpm_tis.c

Hence relying (further) on FEAT_S2FWB.

> and for our testing we used an Ampere Altra Max M128-30 (Neoverse N1
> r3p1, MIDR 0x413fd0c1).

Neoverse N1 systems with the Arm CMN fabric aren’t exactly the right
system to test this. They don’t advertise FEAT_S2FWB but technically
have equivalent semantics.

Once the ISV = 0 syndrome support patches get in, there’ll be a nicer
way than relying on undocumented support for those semantics or relying
on FEAT_S2FWB without querying it, by switching those away from RAM-backed
to an MMIO trap.

Thanks,
-Mohamed

[PATCH 2/3] hw/acpi/tpm: parameterize PPI base address in tpm_build_ppi_acpi

[Mohammadfaiz Bawa]

Add a ppi_base parameter to tpm_build_ppi_acpi() instead of
hardcoding TPM_PPI_ADDR_BASE. This prepares for ARM64 support where
PPI memory is dynamically allocated by the platform bus and the
address is not known at compile time.

Update the x86 ISA TIS caller to pass TPM_PPI_ADDR_BASE explicitly.
No behavioral change.

Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>
---
 hw/acpi/tpm.c         | 8 ++++----
 hw/tpm/tpm_tis_isa.c  | 2 +-
 include/hw/acpi/tpm.h | 3 ++-
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/hw/acpi/tpm.c b/hw/acpi/tpm.c
index cdc022753659af102e56ea4148423b94de1531f6..c4ff2f8cb836c16b00f70865bf55781d5c402aa2 100644
--- a/hw/acpi/tpm.c
+++ b/hw/acpi/tpm.c
@@ -20,7 +20,7 @@
 #include "qapi/error.h"
 #include "hw/acpi/tpm.h"
 
-void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
+void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)
 {
     Aml *method, *field, *ifctx, *ifctx2, *ifctx3, *func_mask,
         *not_implemented, *pak, *tpm2, *tpm3, *pprm, *pprq, *zero, *one;
@@ -40,7 +40,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
      */
     aml_append(dev,
                aml_operation_region("TPP2", AML_SYSTEM_MEMORY,
-                                    aml_int(TPM_PPI_ADDR_BASE + 0x100),
+                                    aml_int(ppi_base + 0x100),
                                     0x5A));
     field = aml_field("TPP2", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
     aml_append(field, aml_named_field("PPIN", 8));
@@ -56,7 +56,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
     aml_append(dev,
                aml_operation_region(
                    "TPP3", AML_SYSTEM_MEMORY,
-                   aml_int(TPM_PPI_ADDR_BASE +
+                   aml_int(ppi_base +
                            0x15a /* movv, docs/specs/tpm.rst */),
                            0x1));
     field = aml_field("TPP3", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
@@ -78,7 +78,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
 
         aml_append(method,
             aml_operation_region("TPP1", AML_SYSTEM_MEMORY,
-                aml_add(aml_int(TPM_PPI_ADDR_BASE), op, NULL), 0x1));
+                aml_add(aml_int(ppi_base), op, NULL), 0x1));
         field = aml_field("TPP1", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
         aml_append(field, aml_named_field("TPPF", 8));
         aml_append(method, field);
diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c
index 61e95434f5b824fa99f0a2aff7f151e87ea631ed..e30bef49558673f4c857c02dae059ce3361a1bc7 100644
--- a/hw/tpm/tpm_tis_isa.c
+++ b/hw/tpm/tpm_tis_isa.c
@@ -162,7 +162,7 @@ static void build_tpm_tis_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
      */
     /* aml_append(crs, aml_irq_no_flags(isadev->state.irq_num)); */
     aml_append(dev, aml_name_decl("_CRS", crs));
-    tpm_build_ppi_acpi(ti, dev);
+    tpm_build_ppi_acpi(ti, dev, TPM_PPI_ADDR_BASE);
     aml_append(scope, dev);
 }
 
diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h
index d2bf6637c5424b92ad99f5baa938fd6cea3520bf..2ab186a7455593df205a7ffecbea2abdfdbd11d5 100644
--- a/include/hw/acpi/tpm.h
+++ b/include/hw/acpi/tpm.h
@@ -20,6 +20,7 @@
 #include "hw/core/registerfields.h"
 #include "hw/acpi/aml-build.h"
 #include "system/tpm.h"
+#include "exec/hwaddr.h"
 
 #ifdef CONFIG_TPM
 
@@ -250,7 +251,7 @@ REG32(CRB_DATA_BUFFER, 0x80)
  */
 #define TPM_I2C_INT_ENABLE_MASK   0x0
 
-void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev);
+void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base);
 
 #endif /* CONFIG_TPM */
 

-- 
2.53.0

Re: [PATCH 2/3] hw/acpi/tpm: parameterize PPI base address in tpm_build_ppi_acpi

[Stefan Berger]

On 3/24/26 3:10 AM, Mohammadfaiz Bawa wrote:
> Add a ppi_base parameter to tpm_build_ppi_acpi() instead of
> hardcoding TPM_PPI_ADDR_BASE. This prepares for ARM64 support where
> PPI memory is dynamically allocated by the platform bus and the
> address is not known at compile time.
> 
> Update the x86 ISA TIS caller to pass TPM_PPI_ADDR_BASE explicitly.
> No behavioral change.
> 
> Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>
> ---
>   hw/acpi/tpm.c         | 8 ++++----
>   hw/tpm/tpm_tis_isa.c  | 2 +-
>   include/hw/acpi/tpm.h | 3 ++-
>   3 files changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/acpi/tpm.c b/hw/acpi/tpm.c
> index cdc022753659af102e56ea4148423b94de1531f6..c4ff2f8cb836c16b00f70865bf55781d5c402aa2 100644
> --- a/hw/acpi/tpm.c
> +++ b/hw/acpi/tpm.c
> @@ -20,7 +20,7 @@
>   #include "qapi/error.h"
>   #include "hw/acpi/tpm.h"
>   
> -void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
> +void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)
>   {
>       Aml *method, *field, *ifctx, *ifctx2, *ifctx3, *func_mask,
>           *not_implemented, *pak, *tpm2, *tpm3, *pprm, *pprq, *zero, *one;
> @@ -40,7 +40,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
>        */
>       aml_append(dev,
>                  aml_operation_region("TPP2", AML_SYSTEM_MEMORY,
> -                                    aml_int(TPM_PPI_ADDR_BASE + 0x100),
> +                                    aml_int(ppi_base + 0x100),
>                                       0x5A));
>       field = aml_field("TPP2", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
>       aml_append(field, aml_named_field("PPIN", 8));
> @@ -56,7 +56,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
>       aml_append(dev,
>                  aml_operation_region(
>                      "TPP3", AML_SYSTEM_MEMORY,
> -                   aml_int(TPM_PPI_ADDR_BASE +
> +                   aml_int(ppi_base +
>                              0x15a /* movv, docs/specs/tpm.rst */),
>                              0x1));
>       field = aml_field("TPP3", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
> @@ -78,7 +78,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)
>   
>           aml_append(method,
>               aml_operation_region("TPP1", AML_SYSTEM_MEMORY,
> -                aml_add(aml_int(TPM_PPI_ADDR_BASE), op, NULL), 0x1));
> +                aml_add(aml_int(ppi_base), op, NULL), 0x1));
>           field = aml_field("TPP1", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
>           aml_append(field, aml_named_field("TPPF", 8));
>           aml_append(method, field);
> diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c
> index 61e95434f5b824fa99f0a2aff7f151e87ea631ed..e30bef49558673f4c857c02dae059ce3361a1bc7 100644
> --- a/hw/tpm/tpm_tis_isa.c
> +++ b/hw/tpm/tpm_tis_isa.c
> @@ -162,7 +162,7 @@ static void build_tpm_tis_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
>        */
>       /* aml_append(crs, aml_irq_no_flags(isadev->state.irq_num)); */
>       aml_append(dev, aml_name_decl("_CRS", crs));
> -    tpm_build_ppi_acpi(ti, dev);
> +    tpm_build_ppi_acpi(ti, dev, TPM_PPI_ADDR_BASE);
>       aml_append(scope, dev);
>   }
>   
> diff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h
> index d2bf6637c5424b92ad99f5baa938fd6cea3520bf..2ab186a7455593df205a7ffecbea2abdfdbd11d5 100644
> --- a/include/hw/acpi/tpm.h
> +++ b/include/hw/acpi/tpm.h
> @@ -20,6 +20,7 @@
>   #include "hw/core/registerfields.h"
>   #include "hw/acpi/aml-build.h"
>   #include "system/tpm.h"
> +#include "exec/hwaddr.h"
>   
>   #ifdef CONFIG_TPM
>   
> @@ -250,7 +251,7 @@ REG32(CRB_DATA_BUFFER, 0x80)
>    */
>   #define TPM_I2C_INT_ENABLE_MASK   0x0
>   
> -void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev);
> +void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base);
>   
>   #endif /* CONFIG_TPM */
>   
> 


Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>

[PATCH 3/3] hw/tpm: add PPI support to tpm-tis-device for ARM64 virt

[Mohammadfaiz Bawa]

Add PPI memory region and ACPI _STA, _DSM to tpm-tis-sysbus so
Windows 11 ARM64 guests no longer log Event ID 15 errors from
tpm.sys on every boot.

Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>
---
 docs/specs/tpm.rst       |  8 +++++---
 hw/arm/virt-acpi-build.c |  9 ++++++++-
 hw/tpm/tpm_tis_sysbus.c  | 11 +++++++++++
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst
index 63cc0b68cd79d64138d4dd05ae158430c6a74643..ba2b0d726745fdf8ebc4c73c9c42e1ff8047a9db 100644
--- a/docs/specs/tpm.rst
+++ b/docs/specs/tpm.rst
@@ -201,9 +201,11 @@ address dynamically at device plug time. The ACPI ``_DSM`` method
 and PPI operation regions reference this dynamically resolved
 address.
 
-PPI is enabled by default and can be controlled with the ``ppi``
-property (e.g. ``-device tpm-tis-device,tpmdev=tpm0,ppi=on``).
-Without PPI support, guest operating systems such as Windows 11
+PPI is controlled by the ``ppi`` property (default ``on``)::
+
+    -device tpm-tis-device,tpmdev=tpm0,ppi=on
+
+Without PPI, guest operating systems such as Windows 11
 ARM64 will log errors when attempting to query TPM Physical
 Presence capabilities via the ACPI ``_DSM`` method.
 
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 719d2f994e65f976f6e754259d0b4f1336f82f13..27a7389a33df221a9dfb0cde1bc35b3ab62e56be 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -240,7 +240,8 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
     Aml *dev = aml_device("TPM0");
     aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
     aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
-    aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+    aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+    aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
 
     Aml *crs = aml_resource_template();
     aml_append(crs,
@@ -248,6 +249,12 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
                                   (uint32_t)memory_region_size(sbdev_mr),
                                   AML_READ_WRITE));
     aml_append(dev, aml_name_decl("_CRS", crs));
+
+    hwaddr ppi_base = platform_bus_get_mmio_addr(pbus, sbdev, 1);
+    if (ppi_base != -1) {
+        ppi_base += pbus_base;
+        tpm_build_ppi_acpi(TPM_IF(sbdev), dev, ppi_base);
+    }
     aml_append(scope, dev);
 }
 #endif
diff --git a/hw/tpm/tpm_tis_sysbus.c b/hw/tpm/tpm_tis_sysbus.c
index e9372e7316305fe1a4d415a712ab516e0fd5f073..f8b63dd4607cacb319e27ea83e421ec5bdc1cb0f 100644
--- a/hw/tpm/tpm_tis_sysbus.c
+++ b/hw/tpm/tpm_tis_sysbus.c
@@ -30,6 +30,7 @@
 #include "hw/core/sysbus.h"
 #include "tpm_tis.h"
 #include "qom/object.h"
+#include "qemu/memalign.h"
 
 struct TPMStateSysBus {
     /*< private >*/
@@ -93,12 +94,14 @@ static void tpm_tis_sysbus_reset(DeviceState *dev)
 static const Property tpm_tis_sysbus_properties[] = {
     DEFINE_PROP_UINT32("irq", TPMStateSysBus, state.irq_num, TPM_TIS_IRQ),
     DEFINE_PROP_TPMBE("tpmdev", TPMStateSysBus, state.be_driver),
+    DEFINE_PROP_BOOL("ppi", TPMStateSysBus, state.ppi_enabled, true),
 };
 
 static void tpm_tis_sysbus_initfn(Object *obj)
 {
     TPMStateSysBus *sbdev = TPM_TIS_SYSBUS(obj);
     TPMState *s = &sbdev->state;
+    size_t host_page_size = qemu_real_host_page_size();
 
     memory_region_init_io(&s->mmio, obj, &tpm_tis_memory_ops,
                           s, "tpm-tis-mmio",
@@ -106,6 +109,12 @@ static void tpm_tis_sysbus_initfn(Object *obj)
 
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+    s->ppi.buf = qemu_memalign(host_page_size,
+                                ROUND_UP(TPM_PPI_ADDR_SIZE, host_page_size));
+    memory_region_init_ram_device_ptr(&s->ppi.ram, obj, "tpm-ppi",
+                                      TPM_PPI_ADDR_SIZE, s->ppi.buf);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->ppi.ram);
 }
 
 static void tpm_tis_sysbus_realizefn(DeviceState *dev, Error **errp)
@@ -122,6 +131,8 @@ static void tpm_tis_sysbus_realizefn(DeviceState *dev, Error **errp)
         error_setg(errp, "'tpmdev' property is required");
         return;
     }
+
+    vmstate_register_ram(&s->ppi.ram, dev);
 }
 
 static void tpm_tis_sysbus_class_init(ObjectClass *klass, const void *data)

-- 
2.53.0

Re: [PATCH 3/3] hw/tpm: add PPI support to tpm-tis-device for ARM64 virt

[Stefan Berger]

On 3/24/26 3:10 AM, Mohammadfaiz Bawa wrote:
> Add PPI memory region and ACPI _STA, _DSM to tpm-tis-sysbus so
> Windows 11 ARM64 guests no longer log Event ID 15 errors from
> tpm.sys on every boot.
> 
> Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>
> ---
>   docs/specs/tpm.rst       |  8 +++++---
>   hw/arm/virt-acpi-build.c |  9 ++++++++-
>   hw/tpm/tpm_tis_sysbus.c  | 11 +++++++++++
>   3 files changed, 24 insertions(+), 4 deletions(-)
> 
> diff --git a/docs/specs/tpm.rst b/docs/specs/tpm.rst
> index 63cc0b68cd79d64138d4dd05ae158430c6a74643..ba2b0d726745fdf8ebc4c73c9c42e1ff8047a9db 100644
> --- a/docs/specs/tpm.rst
> +++ b/docs/specs/tpm.rst
> @@ -201,9 +201,11 @@ address dynamically at device plug time. The ACPI ``_DSM`` method
>   and PPI operation regions reference this dynamically resolved
>   address.
> 
> -PPI is enabled by default and can be controlled with the ``ppi``
> -property (e.g. ``-device tpm-tis-device,tpmdev=tpm0,ppi=on``).
> -Without PPI support, guest operating systems such as Windows 11
> +PPI is controlled by the ``ppi`` property (default ``on``)::
> +
> +    -device tpm-tis-device,tpmdev=tpm0,ppi=on
> +
> +Without PPI, guest operating systems such as Windows 11

This change brings nothing new. It could be in the first patch.

>   ARM64 will log errors when attempting to query TPM Physical
>   Presence capabilities via the ACPI ``_DSM`` method.
> 
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 719d2f994e65f976f6e754259d0b4f1336f82f13..27a7389a33df221a9dfb0cde1bc35b3ab62e56be 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -240,7 +240,8 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
>       Aml *dev = aml_device("TPM0");
>       aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
>       aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
> -    aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> +    aml_append(dev, aml_name_decl("_UID", aml_int(1)));
> +    aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
> 
>       Aml *crs = aml_resource_template();
>       aml_append(crs,
> @@ -248,6 +249,12 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
>                                     (uint32_t)memory_region_size(sbdev_mr),
>                                     AML_READ_WRITE));
>       aml_append(dev, aml_name_decl("_CRS", crs));
> +
> +    hwaddr ppi_base = platform_bus_get_mmio_addr(pbus, sbdev, 1);
> +    if (ppi_base != -1) {
> +        ppi_base += pbus_base;
> +        tpm_build_ppi_acpi(TPM_IF(sbdev), dev, ppi_base);
> +    }
>       aml_append(scope, dev);
>   }
>   #endif
> diff --git a/hw/tpm/tpm_tis_sysbus.c b/hw/tpm/tpm_tis_sysbus.c
> index e9372e7316305fe1a4d415a712ab516e0fd5f073..f8b63dd4607cacb319e27ea83e421ec5bdc1cb0f 100644
> --- a/hw/tpm/tpm_tis_sysbus.c
> +++ b/hw/tpm/tpm_tis_sysbus.c
> @@ -30,6 +30,7 @@
>   #include "hw/core/sysbus.h"
>   #include "tpm_tis.h"
>   #include "qom/object.h"
> +#include "qemu/memalign.h"
> 
>   struct TPMStateSysBus {
>       /*< private >*/
> @@ -93,12 +94,14 @@ static void tpm_tis_sysbus_reset(DeviceState *dev)
>   static const Property tpm_tis_sysbus_properties[] = {
>       DEFINE_PROP_UINT32("irq", TPMStateSysBus, state.irq_num, TPM_TIS_IRQ),
>       DEFINE_PROP_TPMBE("tpmdev", TPMStateSysBus, state.be_driver),
> +    DEFINE_PROP_BOOL("ppi", TPMStateSysBus, state.ppi_enabled, true),
>   };
> 
>   static void tpm_tis_sysbus_initfn(Object *obj)
>   {
>       TPMStateSysBus *sbdev = TPM_TIS_SYSBUS(obj);
>       TPMState *s = &sbdev->state;
> +    size_t host_page_size = qemu_real_host_page_size();
> 
>       memory_region_init_io(&s->mmio, obj, &tpm_tis_memory_ops,
>                             s, "tpm-tis-mmio",
> @@ -106,6 +109,12 @@ static void tpm_tis_sysbus_initfn(Object *obj)
> 
>       sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
>       sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
> +
> +    s->ppi.buf = qemu_memalign(host_page_size,
> +                                ROUND_UP(TPM_PPI_ADDR_SIZE, host_page_size));
> +    memory_region_init_ram_device_ptr(&s->ppi.ram, obj, "tpm-ppi",
> +                                      TPM_PPI_ADDR_SIZE, s->ppi.buf);
> +    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->ppi.ram);
>   }
> 
>   static void tpm_tis_sysbus_realizefn(DeviceState *dev, Error **errp)
> @@ -122,6 +131,8 @@ static void tpm_tis_sysbus_realizefn(DeviceState *dev, Error **errp)
>           error_setg(errp, "'tpmdev' property is required");
>           return;
>       }
> +
> +    vmstate_register_ram(&s->ppi.ram, dev);
>   }
> 
>   static void tpm_tis_sysbus_class_init(ObjectClass *klass, const void *data)
> 

Aside from the documentation part:

Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>