From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60937) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFPgz-0006CH-QQ for qemu-devel@nongnu.org; Tue, 21 Jun 2016 13:42:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFPgx-0001e3-Sy for qemu-devel@nongnu.org; Tue, 21 Jun 2016 13:42:28 -0400 Received: from mail-it0-x241.google.com ([2607:f8b0:4001:c0b::241]:34583) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFPgx-0001dv-O1 for qemu-devel@nongnu.org; Tue, 21 Jun 2016 13:42:27 -0400 Received: by mail-it0-x241.google.com with SMTP id f6so3058989ith.1 for ; Tue, 21 Jun 2016 10:42:27 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <06f042ba-91b2-d751-e53e-6e5ca56081d3@redhat.com> References: <20160618040343.19517-1-bobby.prani@gmail.com> <20160618040343.19517-15-bobby.prani@gmail.com> <06f042ba-91b2-d751-e53e-6e5ca56081d3@redhat.com> From: Pranith Kumar Date: Tue, 21 Jun 2016 13:28:25 -0400 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [RFC v3 PATCH 14/14] target-i386: Generate fences for x86 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: Richard Henderson , Eduardo Habkost , "open list:All patches CC here" , Sergey Fedorov , =?UTF-8?B?QWxleCBCZW5uw6ll?= On Tue, Jun 21, 2016 at 3:28 AM, Paolo Bonzini wrote: > > > On 18/06/2016 06:03, Pranith Kumar wrote: >> Signed-off-by: Pranith Kumar >> --- >> target-i386/translate.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/target-i386/translate.c b/target-i386/translate.c >> index bf33e6b..32b0f5c 100644 >> --- a/target-i386/translate.c >> +++ b/target-i386/translate.c >> @@ -8012,13 +8012,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, >> || (prefixes & PREFIX_LOCK)) { >> goto illegal_op; >> } >> + tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC); >> break; >> case 0xe8 ... 0xef: /* lfence */ >> + tcg_gen_mb(TCG_MO_LD_LD | TCG_BAR_SC); >> + break; > > These are unnecessary. On the other hand, _each and every load_ must be > followed by a LD_LD | LD_ST barrier, and each and every store must be > preceded by a LD_ST | ST_ST barrier. > Reg. the second point, I did consider this situation of running x86 on ARM where such barriers are necessary for correctness. But, I am really apprehensive of the cost it will impose. I am not sure if there are any alternative solutions to avoid generating barriers for each memory operation, but it would be great if we could reduce them. Thanks, -- Pranith