From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33854) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8toj-0000kQ-M5 for qemu-devel@nongnu.org; Fri, 03 Jun 2016 14:27:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b8toh-0006uS-JS for qemu-devel@nongnu.org; Fri, 03 Jun 2016 14:27:32 -0400 Received: from mail-io0-x231.google.com ([2607:f8b0:4001:c06::231]:35975) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8toh-0006uN-CI for qemu-devel@nongnu.org; Fri, 03 Jun 2016 14:27:31 -0400 Received: by mail-io0-x231.google.com with SMTP id k19so69245605ioi.3 for ; Fri, 03 Jun 2016 11:27:31 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <8e9b8569-89a5-845a-a856-7f2fa4435659@twiddle.net> References: <20160531183928.29406-1-bobby.prani@gmail.com> <20160531183928.29406-2-bobby.prani@gmail.com> <57505F1A.3020808@gmail.com> <68c32d50-adc2-25b2-b136-2a486f6b3de7@twiddle.net> <5750995D.6030005@gmail.com> <8e9b8569-89a5-845a-a856-7f2fa4435659@twiddle.net> From: Pranith Kumar Date: Fri, 3 Jun 2016 14:27:01 -0400 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Sergey Fedorov , "open list:All patches CC here" , serge.fdrv@linaro.org, =?UTF-8?B?QWxleCBCZW5uw6ll?= On Thu, Jun 2, 2016 at 5:18 PM, Richard Henderson wrote: > > Hum. That does seem helpful-ish. But I'm not certain how helpful it is to > complicate the helper functions even further. > > What if we have tcg_canonicalize_memop (or some such) split off the barriers > into separate opcodes. E.g. > > MO_BAR_LD_B = 32 // prevent earlier loads from crossing current op > MO_BAR_ST_B = 64 // prevent earlier stores from crossing current op > MO_BAR_LD_A = 128 // prevent later loads from crossing current op > MO_BAR_ST_A = 256 // prevent later stores from crossing current op > MO_BAR_LDST_B = MO_BAR_LD_B | MO_BAR_ST_B > MO_BAR_LDST_A = MO_BAR_LD_A | MO_BAR_ST_A > MO_BAR_MASK = MO_BAR_LDST_B | MO_BAR_LDST_A > > // Match Sparc MEMBAR as the most flexible host. > TCG_BAR_LD_LD = 1 // #LoadLoad barrier > TCG_BAR_ST_LD = 2 // #StoreLoad barrier > TCG_BAR_LD_ST = 4 // #LoadStore barrier > TCG_BAR_ST_ST = 8 // #StoreStore barrier > TCG_BAR_SYNC = 64 // SEQ_CST barrier I really like this format. I would also like to add to the frontend: MO_BAR_ACQUIRE MO_BAR_RELEASE and the following to the backend: TCG_BAR_ACQUIRE TCG_BAR_RELEASE since these are one-way barriers and the previous barrier types do not cover them. > > where > > tcg_gen_qemu_ld_i32(x, y, i, m | MO_BAR_LD_BEFORE | MO_BAR_ST_AFTER) > > emits > > mb TCG_BAR_LD_LD > qemu_ld_i32 x, y, i, m > mb TCG_BAR_LD_ST > > We can then add an optimization pass which folds barriers with no memory > operations in between, so that duplicates are eliminated. > Yes, folding/eliding these barriers in an optimization pass sounds like a good idea. Thanks, -- Pranith