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Iglesias" Date: Thu, 6 Jun 2024 13:55:06 +0200 Message-ID: Subject: Re: [PATCH v2 1/3] hw/dma: Enhance error handling in loading description To: "Fea.Wang" Cc: qemu-devel@nongnu.org, Alistair Francis , Peter Maydell , Jason Wang , "open list:Xilinx Zynq" , Frank Chang Content-Type: multipart/alternative; boundary="000000000000510899061a375b00" Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=edgar.iglesias@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --000000000000510899061a375b00 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Jun 4, 2024 at 9:10=E2=80=AFAM Fea.Wang wrote= : > Loading a description from memory may cause a bus-error. In this > case, the DMA should stop working, set the error flag, and return > the failure value. > > When calling the loading a description function, it should be noticed > that the function may return a failure value. Breaking the loop in this > case is one of the possible ways to handle it. > > Signed-off-by: Fea.Wang > Reviewed-by: Frank Chang > Thanks! Reviewed-by: Edgar E. Iglesias --- > hw/dma/xilinx_axidma.c | 30 ++++++++++++++++++++++++++---- > 1 file changed, 26 insertions(+), 4 deletions(-) > > diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c > index 0ae056ed06..ad307994c2 100644 > --- a/hw/dma/xilinx_axidma.c > +++ b/hw/dma/xilinx_axidma.c > @@ -71,8 +71,11 @@ enum { > enum { > DMASR_HALTED =3D 1, > DMASR_IDLE =3D 2, > + DMASR_SLVERR =3D 1 << 5, > + DMASR_DECERR =3D 1 << 6, > DMASR_IOC_IRQ =3D 1 << 12, > DMASR_DLY_IRQ =3D 1 << 13, > + DMASR_ERR_IRQ =3D 1 << 14, > > DMASR_IRQ_MASK =3D 7 << 12 > }; > @@ -190,17 +193,32 @@ static inline int streamid_from_addr(hwaddr addr) > return sid; > } > > -static void stream_desc_load(struct Stream *s, hwaddr addr) > +static MemTxResult stream_desc_load(struct Stream *s, hwaddr addr) > { > struct SDesc *d =3D &s->desc; > > - address_space_read(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, d, > sizeof *d); > + MemTxResult result =3D address_space_read(&s->dma->as, > + addr, MEMTXATTRS_UNSPECIFIED= , > + d, sizeof *d); > + if (result !=3D MEMTX_OK) { > + if (result =3D=3D MEMTX_DECODE_ERROR) { > + s->regs[R_DMASR] |=3D DMASR_DECERR; > + } else { > + s->regs[R_DMASR] |=3D DMASR_SLVERR; > + } > + > + s->regs[R_DMACR] &=3D ~DMACR_RUNSTOP; > + s->regs[R_DMASR] |=3D DMASR_HALTED; > + s->regs[R_DMASR] |=3D DMASR_ERR_IRQ; > + return result; > + } > > /* Convert from LE into host endianness. */ > d->buffer_address =3D le64_to_cpu(d->buffer_address); > d->nxtdesc =3D le64_to_cpu(d->nxtdesc); > d->control =3D le32_to_cpu(d->control); > d->status =3D le32_to_cpu(d->status); > + return result; > } > > static void stream_desc_store(struct Stream *s, hwaddr addr) > @@ -279,7 +297,9 @@ static void stream_process_mem2s(struct Stream *s, > StreamSink *tx_data_dev, > } > > while (1) { > - stream_desc_load(s, s->regs[R_CURDESC]); > + if (MEMTX_OK !=3D stream_desc_load(s, s->regs[R_CURDESC])) { > + break; > + } > > if (s->desc.status & SDESC_STATUS_COMPLETE) { > s->regs[R_DMASR] |=3D DMASR_HALTED; > @@ -336,7 +356,9 @@ static size_t stream_process_s2mem(struct Stream *s, > unsigned char *buf, > } > > while (len) { > - stream_desc_load(s, s->regs[R_CURDESC]); > + if (MEMTX_OK !=3D stream_desc_load(s, s->regs[R_CURDESC])) { > + break; > + } > > if (s->desc.status & SDESC_STATUS_COMPLETE) { > s->regs[R_DMASR] |=3D DMASR_HALTED; > -- > 2.34.1 > > --000000000000510899061a375b00 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Tue, Jun 4, 2024 at 9:10=E2=80=AFAM Fe= a.Wang <fea.wang@sifive.com&g= t; wrote:
Loading a description from memory may cause a bus-erro= r. In this
case, the DMA should stop working, set the error flag, and return
the failure value.

When calling the loading a description function, it should be noticed
that the function may return a failure value. Breaking the loop in this
case is one of the possible ways to handle it.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>

Thanks!
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
=C2= =A0


---
=C2=A0hw/dma/xilinx_axidma.c | 30 ++++++++++++++++++++++++++----
=C2=A01 file changed, 26 insertions(+), 4 deletions(-)

diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
index 0ae056ed06..ad307994c2 100644
--- a/hw/dma/xilinx_axidma.c
+++ b/hw/dma/xilinx_axidma.c
@@ -71,8 +71,11 @@ enum {
=C2=A0enum {
=C2=A0 =C2=A0 =C2=A0DMASR_HALTED =3D 1,
=C2=A0 =C2=A0 =C2=A0DMASR_IDLE=C2=A0 =3D 2,
+=C2=A0 =C2=A0 DMASR_SLVERR =3D 1 << 5,
+=C2=A0 =C2=A0 DMASR_DECERR =3D 1 << 6,
=C2=A0 =C2=A0 =C2=A0DMASR_IOC_IRQ=C2=A0 =3D 1 << 12,
=C2=A0 =C2=A0 =C2=A0DMASR_DLY_IRQ=C2=A0 =3D 1 << 13,
+=C2=A0 =C2=A0 DMASR_ERR_IRQ=C2=A0 =3D 1 << 14,

=C2=A0 =C2=A0 =C2=A0DMASR_IRQ_MASK =3D 7 << 12
=C2=A0};
@@ -190,17 +193,32 @@ static inline int streamid_from_addr(hwaddr addr)
=C2=A0 =C2=A0 =C2=A0return sid;
=C2=A0}

-static void stream_desc_load(struct Stream *s, hwaddr addr)
+static MemTxResult stream_desc_load(struct Stream *s, hwaddr addr)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0struct SDesc *d =3D &s->desc;

-=C2=A0 =C2=A0 address_space_read(&s->dma->as, addr, MEMTXATTRS_U= NSPECIFIED, d, sizeof *d);
+=C2=A0 =C2=A0 MemTxResult result =3D address_space_read(&s->dma->= ;as,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 addr, MEMTXATTRS_UNSPECIFIED,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 d, sizeof *d);
+=C2=A0 =C2=A0 if (result !=3D MEMTX_OK) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (result =3D=3D MEMTX_DECODE_ERROR) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->regs[R_DMASR] |=3D DMASR_D= ECERR;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 s->regs[R_DMASR] |=3D DMASR_S= LVERR;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->regs[R_DMACR] &=3D ~DMACR_RUNSTOP; +=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->regs[R_DMASR] |=3D DMASR_HALTED;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 s->regs[R_DMASR] |=3D DMASR_ERR_IRQ;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return result;
+=C2=A0 =C2=A0 }

=C2=A0 =C2=A0 =C2=A0/* Convert from LE into host endianness.=C2=A0 */
=C2=A0 =C2=A0 =C2=A0d->buffer_address =3D le64_to_cpu(d->buffer_addre= ss);
=C2=A0 =C2=A0 =C2=A0d->nxtdesc =3D le64_to_cpu(d->nxtdesc);
=C2=A0 =C2=A0 =C2=A0d->control =3D le32_to_cpu(d->control);
=C2=A0 =C2=A0 =C2=A0d->status =3D le32_to_cpu(d->status);
+=C2=A0 =C2=A0 return result;
=C2=A0}

=C2=A0static void stream_desc_store(struct Stream *s, hwaddr addr)
@@ -279,7 +297,9 @@ static void stream_process_mem2s(struct Stream *s, Stre= amSink *tx_data_dev,
=C2=A0 =C2=A0 =C2=A0}

=C2=A0 =C2=A0 =C2=A0while (1) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 stream_desc_load(s, s->regs[R_CURDESC]); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (MEMTX_OK !=3D stream_desc_load(s, s->re= gs[R_CURDESC])) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }

=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (s->desc.status & SDESC_STATUS_= COMPLETE) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->regs[R_DMASR] |=3D DM= ASR_HALTED;
@@ -336,7 +356,9 @@ static size_t stream_process_s2mem(struct Stream *s, un= signed char *buf,
=C2=A0 =C2=A0 =C2=A0}

=C2=A0 =C2=A0 =C2=A0while (len) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 stream_desc_load(s, s->regs[R_CURDESC]); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (MEMTX_OK !=3D stream_desc_load(s, s->re= gs[R_CURDESC])) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }

=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (s->desc.status & SDESC_STATUS_= COMPLETE) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0s->regs[R_DMASR] |=3D DM= ASR_HALTED;
--
2.34.1

--000000000000510899061a375b00--