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Iglesias" Date: Tue, 16 Apr 2024 20:30:59 +0200 Message-ID: Subject: Re: [PATCH RFC] prevent overflow in xlnx_dpdma_desc_get_source_address() To: Alexandra Diupina , "Konrad, Frederic" Cc: Alistair Francis , Alistair Francis , Hyun Kwon , KONRAD Frederic , Peter Maydell , crosthwaitepeter@gmail.com, guillaume.delbergue@greensocs.com, hyunk@xilinx.com, mark.burton@greensocs.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, sdl.qemu@linuxtesting.org Content-Type: multipart/alternative; boundary="0000000000003ae01606163af164" Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=edgar.iglesias@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --0000000000003ae01606163af164 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable + To: Fred On Tue, 16 Apr 2024 at 19:56, Alexandra Diupina wrote: > Peter, thank you! I agree with you that > as mentioned in the documentation > https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field, > we should take 32 bits of the address from one field > (for example, case 1, SRC_ADDR2_EXT - in code it is desc->source_address2= ) > and 16 bits (high or low) of the address from another field > (ADDR_EXT_23 - in code it is desc->address_extension_23, we need [15:0] > bits) > and combine them to make a 48 bit address. > > Therefore, I suggest making the following changes to the code > so that it matches the documentation: > > static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc, > uint8_t frag) > { > uint64_t addr =3D 0; > assert(frag < 5); > > switch (frag) { > case 0: > addr =3D (uint64_t)desc->source_address > + (extract64(desc->address_extension, 16, 16) << 32); > break; > case 1: > addr =3D (uint64_t)desc->source_address2 > + (extract64(desc->address_extension_23, 0, 16) << 32); > break; > case 2: > addr =3D (uint64_t)desc->source_address3 > + (extract64(desc->address_extension_23, 16, 16) << 32); > break; > case 3: > addr =3D (uint64_t)desc->source_address4 > + (extract64(desc->address_extension_45, 0, 16) << 32); > break; > case 4: > addr =3D (uint64_t)desc->source_address5 > + (extract64(desc->address_extension_45, 16, 16) << 32); > break; > default: > addr =3D 0; > break; > } > > return addr; > } > > > This change adds a type cast and also uses extract64() instead of > extract32() > to avoid integer overflow on addition (there was a typo in the previous > letter). > Also in extract64() extracts a bit field with a length of 16 bits > instead of 12, > the shift is changed to 32 so that the extracted field fits into bits > [47:32] of the final address. > > if this calculation is correct, I'm ready to create a second version of > the patch. > > > > > 12/04/24 13:06, Peter Maydell =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > On Fri, 12 Apr 2024 at 09:13, Alexandra Diupina > wrote: > >> Overflow can occur in a situation where desc->source_address > >> has a maximum value (pow(2, 32) - 1), so add a cast to a > >> larger type before the assignment. > >> > >> Found by Linux Verification Center (linuxtesting.org) with SVACE. > >> > >> Fixes: d3c6369a96 ("introduce xlnx-dpdma") > >> Signed-off-by: Alexandra Diupina > >> --- > >> hw/dma/xlnx_dpdma.c | 20 ++++++++++---------- > >> 1 file changed, 10 insertions(+), 10 deletions(-) > >> > >> diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c > >> index 1f5cd64ed1..224259225c 100644 > >> --- a/hw/dma/xlnx_dpdma.c > >> +++ b/hw/dma/xlnx_dpdma.c > >> @@ -175,24 +175,24 @@ static uint64_t > xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc, > >> > >> switch (frag) { > >> case 0: > >> - addr =3D desc->source_address > >> - + (extract32(desc->address_extension, 16, 12) << 20); > >> + addr =3D (uint64_t)(desc->source_address > >> + + (extract32(desc->address_extension, 16, 12) << 20)); > > Unless I'm confused, this cast doesn't help, because we > > will have already done a 32-bit addition of desc->source_address > > and the value from the address_extension part, so it doesn't > > change the result. > > > > If we want to do the addition at 64 bits then using extract64() > > would be the simplest way to arrange for that. > > > > However, I can't figure out what this code is trying to do and > > make that line up with the data sheet; maybe this isn't the > > right datasheet for this device? > > > > https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field > > > > The datasheet suggests that we should take 32 bits of the address > > from one field (here desc->source_address) and 16 bits of the > > address from another (here desc->address_extension's high bits) > > and combine them to make a 48 bit address. But this code is only > > looking at 12 bits of the high 16 in address_extension, and it > > doesn't shift them right enough to put them into bits [47:32] > > of the final address. > > > > Xilinx folks: what hardware is this modelling, and is it > > really the right behaviour? > > > > Also, this device looks like it has a host-endianness bug: the > > DPDMADescriptor struct is read directly from guest memory in > > dma_memory_read(), but the device never does anything to swap > > the fields from guest memory order to host memory order. So > > this is likely broken on big-endian hosts. > > > > thanks > > -- PMM > > > --0000000000003ae01606163af164 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
+ To: Fred

On Tue, 16 Apr 2024 at 19:56, Alexandra Di= upina <adiupina@astralinux.ru<= /a>> wrote:
Peter, thank you! I agree with you= that
as mentioned in the documentation
https://docs.amd.com/r/en-US/u= g1085-zynq-ultrascale-trm/ADDR_EXT-Field,
we should take 32 bits of the address from one field
(for example, case 1, SRC_ADDR2_EXT - in code it is desc->source_address= 2)
and 16 bits (high or low) of the address from another field
(ADDR_EXT_23 - in code it is desc->address_extension_23, we need [15:0] =
bits)
and combine them to make a 48 bit address.

Therefore, I suggest making the following changes to the code
so that it matches the documentation:

static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc, =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 uint8_t frag)
{
=C2=A0=C2=A0=C2=A0=C2=A0 uint64_t addr =3D 0;
=C2=A0=C2=A0=C2=A0=C2=A0 assert(frag < 5);

=C2=A0=C2=A0=C2=A0=C2=A0 switch (frag) {
=C2=A0=C2=A0=C2=A0=C2=A0 case 0:
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 addr =3D (uint64_t)desc-&g= t;source_address
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + = (extract64(desc->address_extension, 16, 16) << 32);
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break;
=C2=A0=C2=A0=C2=A0=C2=A0 case 1:
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 addr =3D (uint64_t)desc-&g= t;source_address2
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + = (extract64(desc->address_extension_23, 0, 16) << 32);
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break;
=C2=A0=C2=A0=C2=A0=C2=A0 case 2:
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 addr =3D (uint64_t)desc-&g= t;source_address3
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + = (extract64(desc->address_extension_23, 16, 16) << 32);
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break;
=C2=A0=C2=A0=C2=A0=C2=A0 case 3:
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 addr =3D (uint64_t)desc-&g= t;source_address4
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + = (extract64(desc->address_extension_45, 0, 16) << 32);
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break;
=C2=A0=C2=A0=C2=A0=C2=A0 case 4:
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 addr =3D (uint64_t)desc-&g= t;source_address5
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 + = (extract64(desc->address_extension_45, 16, 16) << 32);
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break;
=C2=A0=C2=A0=C2=A0=C2=A0 default:
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 addr =3D 0;
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break;
=C2=A0=C2=A0=C2=A0=C2=A0 }

=C2=A0=C2=A0=C2=A0=C2=A0 return addr;
}


This change adds a type cast and also uses extract64() instead of
extract32()
to avoid integer overflow on addition (there was a typo in the previous letter).
Also in extract64() extracts a bit field with a length of 16 bits
instead of 12,
the shift is changed to 32 so that the extracted field fits into bits
[47:32] of the final address.

if this calculation is correct, I'm ready to create a second version of=
the patch.




12/04/24 13:06, Peter Maydell =D0=BF=D0=B8=D1=88=D0=B5=D1=82:
> On Fri, 12 Apr 2024 at 09:13, Alexandra Diupina <adiupina@astralinux.ru> wr= ote:
>> Overflow can occur in a situation where desc->source_address >> has a maximum value (pow(2, 32) - 1), so add a cast to a
>> larger type before the assignment.
>>
>> Found by Linux Verification Center (linuxtesting.org) with SVACE= .
>>
>> Fixes: d3c6369a96 ("introduce xlnx-dpdma")
>> Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
>> ---
>>=C2=A0 =C2=A0hw/dma/xlnx_dpdma.c | 20 ++++++++++----------
>>=C2=A0 =C2=A01 file changed, 10 insertions(+), 10 deletions(-)
>>
>> diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c
>> index 1f5cd64ed1..224259225c 100644
>> --- a/hw/dma/xlnx_dpdma.c
>> +++ b/hw/dma/xlnx_dpdma.c
>> @@ -175,24 +175,24 @@ static uint64_t xlnx_dpdma_desc_get_source_a= ddress(DPDMADescriptor *desc,
>>
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (frag) {
>>=C2=A0 =C2=A0 =C2=A0 =C2=A0case 0:
>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 addr =3D desc->source_address
>> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + (extract32(desc->a= ddress_extension, 16, 12) << 20);
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 addr =3D (uint64_t)(desc->source_a= ddress
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + (extract32(desc->a= ddress_extension, 16, 12) << 20));
> Unless I'm confused, this cast doesn't help, because we
> will have already done a 32-bit addition of desc->source_address > and the value from the address_extension part, so it doesn't
> change the result.
>
> If we want to do the addition at 64 bits then using extract64()
> would be the simplest way to arrange for that.
>
> However, I can't figure out what this code is trying to do and
> make that line up with the data sheet; maybe this isn't the
> right datasheet for this device?
>
> https://docs.amd.com/r/en= -US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field
>
> The datasheet suggests that we should take 32 bits of the address
> from one field (here desc->source_address) and 16 bits of the
> address from another (here desc->address_extension's high bits)=
> and combine them to make a 48 bit address. But this code is only
> looking at 12 bits of the high 16 in address_extension, and it
> doesn't shift them right enough to put them into bits [47:32]
> of the final address.
>
> Xilinx folks: what hardware is this modelling, and is it
> really the right behaviour?
>
> Also, this device looks like it has a host-endianness bug: the
> DPDMADescriptor struct is read directly from guest memory in
> dma_memory_read(), but the device never does anything to swap
> the fields from guest memory order to host memory order. So
> this is likely broken on big-endian hosts.
>
> thanks
> -- PMM


--0000000000003ae01606163af164--