From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D4B9C433E0 for ; Mon, 8 Feb 2021 20:51:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BA1FE64E7A for ; Mon, 8 Feb 2021 20:51:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BA1FE64E7A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39594 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l9DV4-00016r-Ox for qemu-devel@archiver.kernel.org; Mon, 08 Feb 2021 15:51:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58822) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l97cd-0003RM-Pg; Mon, 08 Feb 2021 09:34:46 -0500 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]:45751) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l97cV-0002VH-2U; Mon, 08 Feb 2021 09:34:39 -0500 Received: by mail-ed1-x52c.google.com with SMTP id t5so18295366eds.12; Mon, 08 Feb 2021 06:34:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ml0YDQs56tKj5scJg+obSM9rxRigcfMgWYL0EMd/6L8=; b=s71P9FvWdXO6bwowgAbJCg7+OOycmxOL6n5cdZT51yJ9b4qZaeLN9jp1e4/GOa83Vn LkRHwRIzc+NuRLvyGmBcY3/atFUdNAdo/45KUi8CoE2//ia1a7AbFeRnUAwA3v+OaGyG LnI2cbFxteehoNp+foVjg4PgFM2jLGk024usVSBSHcgBUT0f9k/OhRK5fKT22xyXfbdj XaxJbPBF1Fqn80dUjgeUE8c8+zEzRYyA/0GSrj1FGIIKn3df8S96V67ypEl0GjxB2zdm sv30RPav9LkR9jUdaZgESYq6eHX3Udj+olqGjo7pE/kRH4BvkxlP/HsgCZXbTeWWEhj9 g/jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ml0YDQs56tKj5scJg+obSM9rxRigcfMgWYL0EMd/6L8=; b=mv6yqpmdNrmLgxu93C2xT5dpPxPIQBP7axOfkCWziP3mxJkHHAR1SziEwkwJ34yQGZ DHfKg/0PH4qgP5+IgZdW3cKJQkqRThIpLPjU3FFawwK8gxbjtXejjQeQN0fxJVBR9LPD tuW/d6Rtnc6OemgmAeqzf1/jLSTgf2pRZ+cPnp5oWvNudZGUAYQmoPB4A2bXuDVpELBF IP/S0VOU825+vD5Aywqk3eLs8LXmm03oRY8o+iSz4eSlfl/6oVqgERKGH//ANlZOZQU9 lpN9iumutnVwsRlHHG787dDKwV9jjHUmuIFEUzxJOlwth9dUYOGt1mFNYvTUvThP6pmN 6weA== X-Gm-Message-State: AOAM5331OYFYS0OS6tHvZIoiJx4cNuQwohoYVS3AsGdrRSJSFfpjo/mK zWDlZUvEIwuAhfeefP0LuUyEqkgLWQKiOmSxNO8= X-Google-Smtp-Source: ABdhPJyz4j5ePOKbcNSQhrDPmrgsxo95wmd/cJeJaPGQzn6FMctJjHKr3NaCFSoly55ZrzIYR5y7jy2zwPvcXFQ6aYU= X-Received: by 2002:a50:9dc9:: with SMTP id l9mr17349328edk.377.1612794864223; Mon, 08 Feb 2021 06:34:24 -0800 (PST) MIME-Version: 1.0 References: <1612761924-68000-1-git-send-email-bmeng.cn@gmail.com> <1612761924-68000-3-git-send-email-bmeng.cn@gmail.com> <20210208124425.GI477672@toto> In-Reply-To: From: "Edgar E. Iglesias" Date: Mon, 8 Feb 2021 15:34:13 +0100 Message-ID: Subject: Re: [PATCH v2 2/2] hw/ssi: xilinx_spips: Implement basic QSPI DMA support To: Bin Meng Content-Type: multipart/alternative; boundary="000000000000fa48b605bad41087" Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=edgar.iglesias@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Xuzhou Cheng , Bin Meng , "qemu-devel@nongnu.org Developers" , francisco.iglesias@xilinx.com, qemu-arm , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000fa48b605bad41087 Content-Type: text/plain; charset="UTF-8" On Mon, 8 Feb 2021, 15:10 Bin Meng, wrote: > Hi Edgar, > > On Mon, Feb 8, 2021 at 8:44 PM Edgar E. Iglesias > wrote: > > > > On Mon, Feb 08, 2021 at 01:25:24PM +0800, Bin Meng wrote: > > > From: Xuzhou Cheng > > > > > > ZynqMP QSPI supports SPI transfer using DMA mode, but currently this > > > is unimplemented. When QSPI is programmed to use DMA mode, QEMU will > > > crash. This is observed when testing VxWorks 7. > > > > > > Add a basic implementation of QSPI DMA functionality. > > > > > > Signed-off-by: Xuzhou Cheng > > > Signed-off-by: Bin Meng > > > > + Francisco > > > > Hi, > > > > Like Peter commented on the previous version, the DMA unit is actully > separate. > > Is it really separate? In the Xilinx ZynqMP datasheet, it's an > integrated DMA unit dedicated for QSPI usage. IIUC, other modules on > the ZynqMP SoC cannot use it to do any DMA transfer. To me this is no > different like a DMA engine in a ethernet controller. > Yes, it's a separate module. > > This module is better modelled by pushing data through the Stream > framework > > into the DMA. The DMA model is not upstream but can be found here: > > https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c > > > > What's the benefit of modeling it using the stream framework? > Because it matches real hw and this particular dma exists in various instances, not only in qspi. We don't want duplicate implementations of the same dma. Cheers, Edgar > > Feel free to send a patch to upstream with that model (perhaps changing > > the filename to something more suitable, e.g xlnx-csu-stream-dma.c). > > You can use --author="Edgar E. Iglesias ". > > > > Please, upstream all work Xilinx has done on QEMU. If you think the > DMA support should really be using the Xilinx one, please do the > upstream work as we are not familiar with that implementation. > > Currently we are having a hard time testing the upstream QEMU Xilinx > QSPI model with either U-Boot or Linux. We cannot boot anything with > upstream QEMU with the Xilinx ZynqMP model with the limited > information from the internet. Instructions are needed. I also > suggested to Francisco in another thread that the QEMU target guide > for ZynqMP should be added to provide such information. > > > The DMA should be mapped to 0xFF0F0800 and IRQ 15. > > > > CC:d Francisco, he's going to publish some smoke-tests for this. > > > > Regards, > Bin > --000000000000fa48b605bad41087 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Mon, 8 Feb 2021, 15:10 Bin Meng, <bmeng.cn@gmail= .com> wrote:
Hi Edgar,

On Mon, Feb 8, 2021 at 8:44 PM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> On Mon, Feb 08, 2021 at 01:25:24PM +0800, Bin Meng wrote:
> > From: Xuzhou Cheng <xuzhou.cheng@windriver.= com>
> >
> > ZynqMP QSPI supports SPI transfer using DMA mode, but currently t= his
> > is unimplemented. When QSPI is programmed to use DMA mode, QEMU w= ill
> > crash. This is observed when testing VxWorks 7.
> >
> > Add a basic implementation of QSPI DMA functionality.
> >
> > Signed-off-by: Xuzhou Cheng <xuzhou.cheng@w= indriver.com>
> > Signed-off-by: Bin Meng <bin.meng@windriver.com= >
>
> + Francisco
>
> Hi,
>
> Like Peter commented on the previous version, the DMA unit is actully = separate.

Is it really separate? In the Xilinx ZynqMP datasheet, it's an
integrated DMA unit dedicated for QSPI usage. IIUC, other modules on
the ZynqMP SoC cannot use it to do any DMA transfer. To me this is no
different like a DMA engine in a ethernet controller.

Yes, it's a separa= te module.


> This module is better modelled by pushing data through the Stream fram= ework
> into the DMA. The DMA model is not upstream but can be found here:
> https:/= /github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c
>

What's the benefit of modeling it using the stream framework?


=
Because it matches real hw and this particular dma exists= in various instances, not only in qspi. We don't want duplicate implem= entations of the same dma.=C2=A0

Cheers,=C2=A0
Edgar


> Feel free to send a patch to upstream with that model (perhaps changin= g
> the filename to something more suitable, e.g xlnx-csu-stream-dma.c). > You can use --author=3D"Edgar E. Iglesias <e= dgar.iglesias@xilinx.com>".
>

Please, upstream all work Xilinx has done on QEMU. If you think the
DMA support should really be using the Xilinx one, please do the
upstream work as we are not familiar with that implementation.

Currently we are having a hard time testing the upstream QEMU Xilinx
QSPI model with either U-Boot or Linux. We cannot boot anything with
upstream QEMU with the Xilinx ZynqMP model with the limited
information from the internet. Instructions are needed. I also
suggested to Francisco in another thread that the QEMU target guide
for ZynqMP should be added to provide such information.

> The DMA should be mapped to 0xFF0F0800 and IRQ 15.
>
> CC:d Francisco, he's going to publish some smoke-tests for this. >

Regards,
Bin
--000000000000fa48b605bad41087--