From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:38531)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <mrolnik@gmail.com>) id 1bJR2j-0005UE-A2
	for qemu-devel@nongnu.org; Sat, 02 Jul 2016 15:57:34 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <mrolnik@gmail.com>) id 1bJR2g-0008Jy-Pe
	for qemu-devel@nongnu.org; Sat, 02 Jul 2016 15:57:32 -0400
Received: from mail-wm0-x22f.google.com ([2a00:1450:400c:c09::22f]:36542)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <mrolnik@gmail.com>) id 1bJR2g-0008Jr-ES
	for qemu-devel@nongnu.org; Sat, 02 Jul 2016 15:57:30 -0400
Received: by mail-wm0-x22f.google.com with SMTP id f126so61738632wma.1
	for <qemu-devel@nongnu.org>; Sat, 02 Jul 2016 12:57:30 -0700 (PDT)
MIME-Version: 1.0
In-Reply-To: <CAK4993jakvNJ56T0zMKzMXu-TNbLZUqgZSwd0oXDRVUHf67Zsg@mail.gmail.com>
References: <1467384450-7267-1-git-send-email-mrolnik@gmail.com>
	<d09c116e-ae81-dc94-50b0-90db6118337a@twiddle.net>
	<CAK4993jakvNJ56T0zMKzMXu-TNbLZUqgZSwd0oXDRVUHf67Zsg@mail.gmail.com>
From: Michael Rolnik <mrolnik@gmail.com>
Date: Sat, 2 Jul 2016 22:56:50 +0300
Message-ID: <CAK4993h36Py2Wx7A_6PxMBtFvB+UBUAmdU0XADPPfUkDxOD_GA@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Subject: Re: [Qemu-devel] [PATCH v9 00/10] 8bit AVR cores
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Richard Henderson <rth@twiddle.net>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Peter Maydell <peter.maydell@linaro.org>

for ADIW, SBIW instructions I modified address calculation.

On Sat, Jul 2, 2016 at 9:20 PM, Michael Rolnik <mrolnik@gmail.com> wrote:

> Hi Richard.
>
> I folded all my changes into prevous commits.
>
> 1. I meant EOR, which is actually XOR. Prevously it did not save the
> result into the register
> 2. my mistake I meant ORI and LDS and not ADIW, SBIW
> 3. when there is a call to tlb_fill for [0x0000: 0x0100) region it
>     a. sets env->fullwr
>     b. calls cpu_loop_exit_restore.
>     c. the whole block is retranslated and instead of st it generates
> helper_fullwr for each store within this TB.
>     d. helper_fullwr calls cpu_physical_memory_write
>     e. sample_io_write is called and register is changed since the whole
> thing is done from within a helper
>     f. this is tested.
>
>
> On Fri, Jul 1, 2016 at 10:09 PM, Richard Henderson <rth@twiddle.net>
> wrote:
>
>> On 07/01/2016 07:47 AM, Michael Rolnik wrote:
>>
>>> 5. translation bug fixes for ADIW, SBIW, XOR instructions
>>> 6. propper handling of cpu register writes though memory
>>>
>>
>> I don't see these changes in the patch set.
>>
>>
>> r~
>>
>
>
>
> --
> Best Regards,
> Michael Rolnik
>



-- 
Best Regards,
Michael Rolnik